Cadence
131 open semiconductor roles on SiliconBoard
Open positions at Cadence
Associate Sales Administrator (1 year contractor)
ZHUBEI 01
Chip Lead / Physical Design Director
2 Locations
Design Engineering Architect
San Jose, CA
Senior Design Engineer -Memory Controller IP
San Jose, CA
Lead Design Engineer
San Jose, CA
Design Engineer II
Mount Royal, NJ
Lead Software Engineer (Computational Electromagnetics, Numerical Analysis, Field Solver)
San Jose, CA
Lead Analog IC Designer
San Jose, CA
Principal Analog I.C Engineer
San Jose, CA
Application Engineer Manager – Formal Verification and Functional Simulation
Belo Horizonte, Brazil, South America
Physical Design Engineer (PNR/Physical Verification/STA/EMIR)
Mount Royal, NJ
Principal Product Engineer, System Verification, Emulation (R54514/ad)
San Jose, CA
Sr. Principal AE - Verification IP, HPC Protocols
San Jose, CA
Design Verification Lead Engineer
Austin, TX
Principal Analog IC Design Engineer, High Speed SerDes
San Jose, CA
Principal Product Engineer System Verification, Emulation
San Jose, United States, North America
Lead Product Engineer - Genus & Innovus
Shanghai, China, Asia
Lead Customer Engagement Engineer- Liberate
Shanghai, China, Asia
Senior Principal Software Engineer - Compiler Development (R54563/fm)
Burlington, MA
Principal Product Engineer System Verification, Emulation
San Jose, CA
Mixed Signal Systems and Verification Engineer II
Toronto, Canada, North America
Principal Product Engineer - Innovus
Seoul, South Korea, Asia
ATE Test Engineering Architect
San Jose, United States, North America
Digital Verification Intern
WARSZAWA
Design Engineering Architect
Austin, TX
Application Engineer – JedAI/Pulse Installation & Enablement
HOME CA
Principal Applied ML Engineer
San Jose, CA
Intern: Application Engineering - Silicon Signoff and Verification
Belo Horizonte, Brazil, South America
DSP or Serdes RTL Sr Principal Digital Design Engineer
San Jose, CA
Sr Principal Emulation Application Engineer
San Jose, CA
Lead Solutions Engineer – Runset Enablement (Physical Verification)
Austin, TX
IC Verification AI Application Engineer
San Jose, CA
Senior Principal IC Design Verification Application Engineer
San Jose, CA
DSP or Serdes RTL Sr Principal Digital Design Engineer
San Jose, CA
Sr Principal Emulation Application Engineer
San Jose, CA
Senior Principal IC Design Verification Application Engineer
San Jose, CA
IC Verification AI Application Engineer
San Jose, CA
Lead Solutions Engineer – Runset Enablement (Physical Verification)
Austin, TX
Sr IC DV Emulation/Prototyping AE
2 Locations
Jasper Formal Verification - Sr Principal Application Engineer
2 Locations
Lead Solutions Engineer – Runset Enablement (Physical Verification)
San Jose, CA
Lead Solutions Engineer – Runset Enablement (Physical Verification)
San Jose, CA
Product Validation Engineer (Analog Circuit Design)
San Jose, CA
Software Architect, Physical Verification
San Jose, United States, North America
Principal Education Application Engineer- System Verification Expert
Bangalore, India, Asia
Verification Field Application Engineer - Simulation - San Jose, CA
San Jose, CA
Analog CAD Engineering specialist
Maryland, United States
Principal Product Engineer (Analog Design Automation)
San Jose, CA
Principal Product Engineer (Analog Design Automation)
San Jose, CA
Analog CAD Engineering specialist
Maryland, United States
Analog CAD Engineering specialist
Cary, NC
Analog CAD Engineering specialist
Cary, NC
Analog CAD Engineering specialist
Mount Royal, NJ
Application Engineer I: Analog IC Design and Layout
Belo Horizonte, Brazil, South America
Application Engineer I: Digital Verification & Simulation
Belo Horizonte, Brazil, South America
Lead Software Engineer ( Verification )
Bangalore, India, Asia
Applied ML – Functional Verification Engineer
San Jose, CA
Applied ML - Functional Verification Engineer
San Jose, CA
Strategic Sourcing Specialist
San Jose, United States, North America
Principal Software Engineer ( Verification )
Ahmedabad, India, Asia
Senior Distributed Systems Engineer - EDA/VLSI Platform
San Jose, CA
Sr. Principal Functional Verification Engineer: Applied ML
Belo Horizonte, Brazil, South America
Mixed Signal IP - Senior Program Manager
4 Locations
Design Engineer I
San Jose, United States, North America
Analog/Mixed Signal Lead CAD Engineer
Shanghai, China, Asia
Applied ML – Lead Functional Verification Engineer
Petah Tikva, Israel, Middle East
Applied ML – Senior Principal Functional Verification Engineer
Petah Tikva, Israel, Middle East
Application Engineering Director - IC Design Verification
San Jose, United States, North America
Sr Principal Emulation Application Engineer
San Jose, United States, North America
DFT Design Engineer
Austin, United States, North America
Corporate Counsel - Employment
San Jose, United States, North America
Senior Emulation/Verification Application Engineer
San Jose, United States, North America
IC Design Verification Application Engineer
San Jose, United States, North America
Senior Principal IC Design Verification Application Engineer
San Jose, United States, North America
Lead Digital Verification Engineer
Edinburgh, UK, Europe
Analog/Mixed-Signal IC Design Co-Op/Intern (Summer 2026) / Stage/Co-Op en Conception de CI Analogiques/Signal Mixte (Été 2026)
Montreal, Canada, North America
Lead Application Engineer – Custom IC Design and Implementation
San Jose, United States, North America
AE Director Emulation and Prototyping
San Jose, United States, North America
Lead Product Engineer: System Verification and Emulation
Belo Horizonte, Brazil, South America
Product Engineer II – System Verification and Emulation
Belo Horizonte, Brazil, South America
Sr Principal Test Engineer
Hsinchu, Taiwan, Asia
Sr. Principal AE - Verification IP, HPC Protocols
San Jose, United States, North America
Physical Design Engineer (PNR/Physical Verification/STA/EMIR)
Montreal, Canada, North America
SoC architect
Austin, United States, North America
Principal Product Engineer (Analog Design Automation)
San Jose, United States, North America
Application Engineer, RTL2GDS Architect
San Jose, United States, North America
Lead Design Engineer - Physical Design
Beijing, China, Asia
DFT Design Engineer
Austin, United States, North America
Lead Product Engineer - Innovus
Seoul, South Korea, Asia
RTL-GDSII, Sr Application Engineer
San Jose, United States, North America
SoC, IP Global Account Group Director
San Jose, United States, North America
SoC, Foundry, Strategic Business Development Director
San Jose, United States, North America
Lead Verification Engineer
Noida, India, Asia
Sr Principal Verification Engineer
Noida, India, Asia
Senior Distributed Systems Engineer - EDA/VLSI Platform
San Jose, United States, North America
Applied ML - Functional Verification Engineer
San Jose, United States, North America
Applied ML – Functional Verification Engineer
San Jose, United States, North America
Lead Software Engineer, DFT/ATPG
Austin, United States, North America
Associate Payroll Analyst
Bracknell, UK, Europe
Principal Verification Engineer
Cork, Ireland, Europe
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