C
Principal Product Engineer
Accepting applicationsCadence · Noida, Uttar Pradesh, India
Full-Time Mid_senior ASICATPGBoundary ScanCadenceDFT
Estimated market salary
₹7-13 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
India
Cadence Design Systems is looking for a highly motivated engineer to be part of the Modus R&D team, with a focus on validating and supporting Design-for-test (DFT) technologies. Candidate must have 7+ years of experience in DFT/ATPG/ASIC Design flows and knowledge of RTL Verilog/VHDL coding styles, Synthesis. This position requires excellent communication skills (written and oral) to interface with Product Engineers (PEs) and R&D and will occasionally also involve direct customer support responsibilities. Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability.
Role Responsibility
Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Boundary Scan, Compression, RTL DFT, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs.
Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool.
Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues.
Debug issues reported by customers and suggest/implement measures to plug the gaps.
Position Requirements
Candidate is expected to be:
B.E/M.E. in Electronics/Electrical
Strong in Digital electronics, Verilog
Good understanding of DFT techniques and methodologies
Familiarity with Test standards like 1149.1, 1500, 1687 is a plus
Experience with Cadence Test or other Test tools is preferred
Good scripting skills (Tcl, Perl)
Strong analysis and problem solving skills
Good communication skills are a must
Keen & quick learner ready to learn new things with little guidance & take up challenging tasks
This position is in Product Validation Team of Cadence Modus DFT Software Solution.
Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design process.
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Role Responsibility
Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Boundary Scan, Compression, RTL DFT, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs.
Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool.
Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues.
Debug issues reported by customers and suggest/implement measures to plug the gaps.
Position Requirements
Candidate is expected to be:
B.E/M.E. in Electronics/Electrical
Strong in Digital electronics, Verilog
Good understanding of DFT techniques and methodologies
Familiarity with Test standards like 1149.1, 1500, 1687 is a plus
Experience with Cadence Test or other Test tools is preferred
Good scripting skills (Tcl, Perl)
Strong analysis and problem solving skills
Good communication skills are a must
Keen & quick learner ready to learn new things with little guidance & take up challenging tasks
This position is in Product Validation Team of Cadence Modus DFT Software Solution.
Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design process.
Show more Show less