C
Verification Lead
Accepting applicationsCadence · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogUVMVerification
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
5d ago
Category
Verification
Experience
Mid_senior
Country
India
About the Company
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
About the Role
Cadence Bangalore is looking for a Principal/Senior Principal Verification Engineer.
Responsibilities
Requires 8-18 years of experience in the VLSI domain, with a Master’s or Bachelor’s degree in engineering.
Strong expertise in Verilog, HVL (SV, Specman e) with UVM/OVM/eRM methodology is essential.
Proficiency in assertions development/closure, constraint randomization, functional and code coverages, and formal verification is required.
Expertise in test-bench development is necessary.
Strong RTL and GLS (with or without SDF) simulation debug skills are needed.
Ability to manage project schedules and delivery independently is important.
Proficiency in Perl/Tcl scripting and automation is also required.
Qualifications
Master’s or Bachelor’s degree in engineering.
Required Skills
Strong expertise in Verilog, HVL (SV, Specman e) with UVM/OVM/eRM methodology.
Proficiency in assertions development/closure, constraint randomization, functional and code coverages, and formal verification.
Expertise in test-bench development.
Strong RTL and GLS (with or without SDF) simulation debug skills.
Proficiency in Perl/Tcl scripting and automation.
Preferred Skills
Experience in managing project schedules and delivery independently.
Pay range and compensation package
Not specified in the job description.
.
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Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
About the Role
Cadence Bangalore is looking for a Principal/Senior Principal Verification Engineer.
Responsibilities
Requires 8-18 years of experience in the VLSI domain, with a Master’s or Bachelor’s degree in engineering.
Strong expertise in Verilog, HVL (SV, Specman e) with UVM/OVM/eRM methodology is essential.
Proficiency in assertions development/closure, constraint randomization, functional and code coverages, and formal verification is required.
Expertise in test-bench development is necessary.
Strong RTL and GLS (with or without SDF) simulation debug skills are needed.
Ability to manage project schedules and delivery independently is important.
Proficiency in Perl/Tcl scripting and automation is also required.
Qualifications
Master’s or Bachelor’s degree in engineering.
Required Skills
Strong expertise in Verilog, HVL (SV, Specman e) with UVM/OVM/eRM methodology.
Proficiency in assertions development/closure, constraint randomization, functional and code coverages, and formal verification.
Expertise in test-bench development.
Strong RTL and GLS (with or without SDF) simulation debug skills.
Proficiency in Perl/Tcl scripting and automation.
Preferred Skills
Experience in managing project schedules and delivery independently.
Pay range and compensation package
Not specified in the job description.
.
Show more Show less