C
Principal Analog design Engineer
Accepting applicationsCadence · Hyderabad, Telangana, India
Full-Time Mid_senior AnalogCadenceEDA
Estimated market salary
₹15-28 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Design
Experience
Mid_senior
Country
India
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantag
eThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact
.Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees
.The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer succes
sMultiple avenues of learning and development available for employees to explore as per their specific requirement and interest
sYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every da
y
Location: Hyderabad/PUNE/NOI
DA
Job Descrip
tionRole Sum
maryWe are looking for an experienced Principal Analog Design Engineer to drive the design and delivery of high‑speed interface IPs, with a strong emphasis on Die‑to‑Die (D2D) interconnects based on the UCIe standard and advanced package technologies. The role requires hands‑on ownership from architecture through silicon bring‑up, working closely with layout, verification, package, and system te
ams.
Key Responsibil
itiesArchitect, design, and deliver high‑speed analog / mixed‑signal circuits for Die‑to‑Die and chiplet‑based systems, including UCIe‑compliant interf
aces.Own analog blocks for high‑speed interfaces such as clocking, TX/RX front‑ends, termination schemes, biasing, and equalization support circ
uits.Drive architecture definition, feasibility analysis, and design trade‑offs considering signal integrity, power, noise, and packaging parasi
tics.Perform schematic design, simulation, and optimization across PVT corners using industry‑standard EDA t
ools.Work closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to co‑optimize circuit and package de
sign.Support layout reviews, parasitic extraction analysis, and post‑layout sign‑off for high‑speed perform
ance.Collaborate with AMS verification, digital, and system teams to enable full‑chip integration and valida
tion.Participate in silicon bring‑up, debug, and characterization, including correlation with simulation res
ults.Contribute to design methodology, checklists, and best practices for high‑speed analog and D2D des
igns.
Required Qualific
ationsBachelor’s or Master’s degree in Electrical / Electronics Engineering or related
field.8+ years of hands‑on experience in analog / mixed‑signal IC d
esign.Strong experience with high‑speed interface design (e.g., DDR, PCIe, SerDes, Die‑to‑Die l
inks).Solid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architec
tures.Experience working with advanced packaging technologies and understanding package‑induced effects on high‑speed sign
aling.Proficiency in schematic‑level design, simulation, and debug across PVT co
rners.Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clo
cking.
Preferred / Nice‑to‑Have
SkillsDirect hands‑on experience with UCIe PHY design or integ
ration.Exposure to AMS verification flows and mixed‑signal simulation enviro
nments.Experience with post‑silicon debug and corre
lation.Knowledge of power integrity, thermal considerations, and package‑aware design
flows.Ability to mentor junior engineers and lead technical discu
ssions.
What Success Lo
oks LikeRobust, scalable UCIe / D2D analog IPs meeting performance, power, and reliability
targets.Smooth collaboration across design, verification, and packagin
g teams.Predictable execution aligned with project milestones and KPIs
/ OKRs.Strong ownership mindset from architecture to
silicon.
Show more Show less
The Cadence Advantag
eThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact
.Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees
.The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer succes
sMultiple avenues of learning and development available for employees to explore as per their specific requirement and interest
sYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every da
y
Location: Hyderabad/PUNE/NOI
DA
Job Descrip
tionRole Sum
maryWe are looking for an experienced Principal Analog Design Engineer to drive the design and delivery of high‑speed interface IPs, with a strong emphasis on Die‑to‑Die (D2D) interconnects based on the UCIe standard and advanced package technologies. The role requires hands‑on ownership from architecture through silicon bring‑up, working closely with layout, verification, package, and system te
ams.
Key Responsibil
itiesArchitect, design, and deliver high‑speed analog / mixed‑signal circuits for Die‑to‑Die and chiplet‑based systems, including UCIe‑compliant interf
aces.Own analog blocks for high‑speed interfaces such as clocking, TX/RX front‑ends, termination schemes, biasing, and equalization support circ
uits.Drive architecture definition, feasibility analysis, and design trade‑offs considering signal integrity, power, noise, and packaging parasi
tics.Perform schematic design, simulation, and optimization across PVT corners using industry‑standard EDA t
ools.Work closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to co‑optimize circuit and package de
sign.Support layout reviews, parasitic extraction analysis, and post‑layout sign‑off for high‑speed perform
ance.Collaborate with AMS verification, digital, and system teams to enable full‑chip integration and valida
tion.Participate in silicon bring‑up, debug, and characterization, including correlation with simulation res
ults.Contribute to design methodology, checklists, and best practices for high‑speed analog and D2D des
igns.
Required Qualific
ationsBachelor’s or Master’s degree in Electrical / Electronics Engineering or related
field.8+ years of hands‑on experience in analog / mixed‑signal IC d
esign.Strong experience with high‑speed interface design (e.g., DDR, PCIe, SerDes, Die‑to‑Die l
inks).Solid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architec
tures.Experience working with advanced packaging technologies and understanding package‑induced effects on high‑speed sign
aling.Proficiency in schematic‑level design, simulation, and debug across PVT co
rners.Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clo
cking.
Preferred / Nice‑to‑Have
SkillsDirect hands‑on experience with UCIe PHY design or integ
ration.Exposure to AMS verification flows and mixed‑signal simulation enviro
nments.Experience with post‑silicon debug and corre
lation.Knowledge of power integrity, thermal considerations, and package‑aware design
flows.Ability to mentor junior engineers and lead technical discu
ssions.
What Success Lo
oks LikeRobust, scalable UCIe / D2D analog IPs meeting performance, power, and reliability
targets.Smooth collaboration across design, verification, and packagin
g teams.Predictable execution aligned with project milestones and KPIs
/ OKRs.Strong ownership mindset from architecture to
silicon.
Show more Show less