GF
Principal Product Engineer
Accepting applicationsGyga Force · Fremont, CA
Full-Time Mid_senior ATEDDRDFTPythonmentor
Posted
5d ago
Category
Manufacturing
Experience
Mid_senior
Country
United States
Our client is an innovative semiconductor company developing next-generation memory technologies for mission-critical computing, embedded, and high-reliability applications where performance and data integrity are paramount.
They are seeking a principal-level engineer to own advanced memory products from first silicon through high-volume manufacturing—bridging circuit design expertise with hands-on silicon validation, characterization, and product engineering. This is a high-visibility role reporting directly to the VP of Engineering.
RESPONSIBILITIES:
Own silicon bring-up, validation, and characterization at both wafer and packaged device levels, including hands-on lab debug using oscilloscopes and related instrumentation.
Contribute to the design and review of memory and high-speed interface circuits (including DDR4/DDR5), with emphasis on interface timing analysis, signal integrity, and design-for-testability.
Correlate silicon characterization results with simulation to identify discrepancies and drive design improvements.
Lead debug and failure analysis spanning silicon, package, and system levels.
Collaborate closely with circuit design teams to understand architecture and implementation, identify design-related issues in DDR and other high-speed interfaces, and drive corrective action.
Define and refine test methodologies, coverage plans, and production screening strategies.
Champion design-for-test (DFT) practices to improve observability, debug efficiency, and manufacturing yield.
Analyze yield data and drive continuous yield improvement across wafer fabrication, packaging, and final test.
Own production ramp and sustaining engineering for high-volume manufacturing.
Prepare and present technical reports on performance, reliability, and yield trends to executive leadership.
Provide technical leadership and mentor engineers across design, test, packaging, and manufacturing teams.
REQUIRED QUALIFICATIONS:
M.S. or Ph.D. in Electrical Engineering or a closely related discipline.
8+ years of experience in semiconductor product, test, or design engineering.
Strong background in memory products and high-speed interface circuits, particularly DDR4/DDR5, including interface timing analysis, signal integrity, and high-speed I/O behavior.
Hands-on experience with silicon bring-up, wafer-level test, ATE, and failure analysis.
Ability to interpret design specifications and schematics and troubleshoot design-related issues at both silicon and system levels.
Demonstrated track record in characterization, yield improvement, and high-volume manufacturing support.
Proven ability to take ownership of technically complex problems and drive them to resolution.
PREFERRED QUALIFICATIONS:
Familiarity with MRAM or other emerging non-volatile memory technologies.
Broad understanding of memory technologies, including DRAM, SRAM, NAND, and emerging memory architectures.
Experience with system-in-package (SiP) or multi-die integration, including exposure to advanced packaging technologies such as 2.5D/3D integration, interposers, or heterogeneous integration.
Proficiency with data analysis tools such as Python, JMP, or equivalent.
INCENTIVES & BENEFITS:
Up to 250K base salary (depending on experience).
4 weeks of annual PTO plus U.S. holidays.
Equity via stock options.
Performance-based bonus.
Comprehensive Medical, Dental, Vision, and Life Insurance.
401(k).
Relocation assistance may be available for an exceptional candidate.
For a list of all our openings, please visit www.gygaforce.com
Show more Show less
They are seeking a principal-level engineer to own advanced memory products from first silicon through high-volume manufacturing—bridging circuit design expertise with hands-on silicon validation, characterization, and product engineering. This is a high-visibility role reporting directly to the VP of Engineering.
RESPONSIBILITIES:
Own silicon bring-up, validation, and characterization at both wafer and packaged device levels, including hands-on lab debug using oscilloscopes and related instrumentation.
Contribute to the design and review of memory and high-speed interface circuits (including DDR4/DDR5), with emphasis on interface timing analysis, signal integrity, and design-for-testability.
Correlate silicon characterization results with simulation to identify discrepancies and drive design improvements.
Lead debug and failure analysis spanning silicon, package, and system levels.
Collaborate closely with circuit design teams to understand architecture and implementation, identify design-related issues in DDR and other high-speed interfaces, and drive corrective action.
Define and refine test methodologies, coverage plans, and production screening strategies.
Champion design-for-test (DFT) practices to improve observability, debug efficiency, and manufacturing yield.
Analyze yield data and drive continuous yield improvement across wafer fabrication, packaging, and final test.
Own production ramp and sustaining engineering for high-volume manufacturing.
Prepare and present technical reports on performance, reliability, and yield trends to executive leadership.
Provide technical leadership and mentor engineers across design, test, packaging, and manufacturing teams.
REQUIRED QUALIFICATIONS:
M.S. or Ph.D. in Electrical Engineering or a closely related discipline.
8+ years of experience in semiconductor product, test, or design engineering.
Strong background in memory products and high-speed interface circuits, particularly DDR4/DDR5, including interface timing analysis, signal integrity, and high-speed I/O behavior.
Hands-on experience with silicon bring-up, wafer-level test, ATE, and failure analysis.
Ability to interpret design specifications and schematics and troubleshoot design-related issues at both silicon and system levels.
Demonstrated track record in characterization, yield improvement, and high-volume manufacturing support.
Proven ability to take ownership of technically complex problems and drive them to resolution.
PREFERRED QUALIFICATIONS:
Familiarity with MRAM or other emerging non-volatile memory technologies.
Broad understanding of memory technologies, including DRAM, SRAM, NAND, and emerging memory architectures.
Experience with system-in-package (SiP) or multi-die integration, including exposure to advanced packaging technologies such as 2.5D/3D integration, interposers, or heterogeneous integration.
Proficiency with data analysis tools such as Python, JMP, or equivalent.
INCENTIVES & BENEFITS:
Up to 250K base salary (depending on experience).
4 weeks of annual PTO plus U.S. holidays.
Equity via stock options.
Performance-based bonus.
Comprehensive Medical, Dental, Vision, and Life Insurance.
401(k).
Relocation assistance may be available for an exceptional candidate.
For a list of all our openings, please visit www.gygaforce.com
Show more Show less