Celero Communications
6 open semiconductor roles on SiliconBoard
Open positions at Celero Communications
Principal Design Validation & Test (DVT) Engineer
Irvine, CA
Full-Time Senior Test
Senior/Principal Full-Chip Physical Verification Engineer
San Jose, CA
Full-Time Senior Verification
Principal/Senior High-Speed Analog Layout Engineer
Irvine, CA
Full-Time Principal Design
Principal Physical Design Engineer
San Jose, CA
Full-Time Principal Design
SerDes Lead Designer
Irvine, CA
Full-Time Mid-senior Test
Analog Design Engineer
Irvine, United States, North America
Full-Time Senior Design