CC
Principal Physical Design Engineer
Accepting applicationsCelero Communications · San Jose, CA
Full-Time Principal AICalibrePythonTclanalog
Posted
15 Jun
Category
Design
Experience
Principal
Country
United States
About The Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.
We are seeking a Principal Physical Design Engineer to be part of our team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects of Physical Verification on advanced TSMC nodes. Candidates have completed multiple successful tapeouts. Candidates be able to drive methodology, quality, and predictable delivery across multiple programs. You will partner closely with analog design team and PD team to ensure designs meet aggressive manufacturability, and schedule goals.
Locations: San Jose, CA and Irvine, CA
Key Responsibilities
Team & Project Leadership
Lead full chip Physical Verification effort
Own execution plans, schedules for full-chip
Drive accountability for quality, milestones, and tapeout readiness.
Conduct full chip and blocks PV checks
Physical Verification Ownership
Ownership of full chip verification
Work with internal analog team to ensure clean IP delivery
Responsible for running and analyzing DRC/ERC/LUP/PERC results
Experience with using either ICV or Calibre verification tools
Understanding advance TSMC DRC rules
Cross-Functional Collaboration
Partner with analog, block, chip top owners to ensure clean floorplan
Provide early guidance on corner case requirements
Influence floorplan constraints, hierarchy, and implementation strategy.
Participate in tapeout readiness reviews.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering or related field.
10+ years of experience with full chip verifications
Proven hands-on experience with:
Physical Verification tool (ICV/Calibre)
Able to assemble a flow to support block/chip level PV
Strong expertise in:
Floorplanning to avoid DRC/LVS issues
Provide guidance to analog IP team to allow for clean integration
Preferred Qualifications
Experience in advanced technology nodes (7nm, 5nm, 3nm).
Automation skills using Tcl, Python, or shell scripting.
Salary Range
$150,000 - $250,000 Base Annually
The final offer will be determined based on job-related skills, experience, qualifications, and location.
Show more Show less
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.
We are seeking a Principal Physical Design Engineer to be part of our team delivering complex digital blocks and full-chip implementations in advanced process nodes. This role owns execution of all aspects of Physical Verification on advanced TSMC nodes. Candidates have completed multiple successful tapeouts. Candidates be able to drive methodology, quality, and predictable delivery across multiple programs. You will partner closely with analog design team and PD team to ensure designs meet aggressive manufacturability, and schedule goals.
Locations: San Jose, CA and Irvine, CA
Key Responsibilities
Team & Project Leadership
Lead full chip Physical Verification effort
Own execution plans, schedules for full-chip
Drive accountability for quality, milestones, and tapeout readiness.
Conduct full chip and blocks PV checks
Physical Verification Ownership
Ownership of full chip verification
Work with internal analog team to ensure clean IP delivery
Responsible for running and analyzing DRC/ERC/LUP/PERC results
Experience with using either ICV or Calibre verification tools
Understanding advance TSMC DRC rules
Cross-Functional Collaboration
Partner with analog, block, chip top owners to ensure clean floorplan
Provide early guidance on corner case requirements
Influence floorplan constraints, hierarchy, and implementation strategy.
Participate in tapeout readiness reviews.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering or related field.
10+ years of experience with full chip verifications
Proven hands-on experience with:
Physical Verification tool (ICV/Calibre)
Able to assemble a flow to support block/chip level PV
Strong expertise in:
Floorplanning to avoid DRC/LVS issues
Provide guidance to analog IP team to allow for clean integration
Preferred Qualifications
Experience in advanced technology nodes (7nm, 5nm, 3nm).
Automation skills using Tcl, Python, or shell scripting.
Salary Range
$150,000 - $250,000 Base Annually
The final offer will be determined based on job-related skills, experience, qualifications, and location.
Show more Show less
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