CC

Analog Design Engineer

Accepting applications

Celero Communications · Irvine, United States, North America

Full-Time Senior AIAnalogFinFetaianalog
Posted
4 Apr
Category
Design
Experience
Senior
Country
United States

About the job:


Are you an Analog Design Engineer, Principal who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology powering next generation AI? We are looking for an Analog Design Engineer – someone who is excited to join a fast-growing Start-Up Company growing a group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!


Locations Available: Irvine, CA HQ, San Jose, CA, Austin, TX, Ottawa Ontario, CN, & Vancouver


Candidate will have the opportunity to architect and design circuits for high performance transceivers and other critical analog functions.


What You Will Do:

  • High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.).
  • Clock generation and distribution (VCOs, PLL, clock distribution, etc)
  • Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc)
  • New techniques for the development of next generation optical transceiver
  • Design of custom passive components, from concept to silicon implementation
  • Supervise analog layouts within advanced process nodes
  • System verification and circuit design spec creation
  • Silicon bring-up, debug and support
  • Team communication and documentation


What You Will Bring:

  • Master’s degree and/or PhD (preferred) in Electrical Engineering or related fields with 5+ years of experience.
  • Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks.
  • Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
  • Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other)
  • Knowledge of the fundamentals on electromagnetism, lump models and high frequency design
  • Good understanding of analog layouts in FinFet and its effect on high-speed designs is a plus
  • Experienced in lab chip bring-up and debugging efforts is a plus
  • Strong communication and documentation skills


Salary Range

$150,000 - $250,000 Base Annually

The final offer will be determined based on job-related skills, experience, qualifications, and location.