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Staff/Principal Analog IC Design Engineer
Accepting applicationsOptalysys · Bengaluru, Karnataka, India
Full-Time Mid_senior AnalogCMOSCadenceFinFETMixed-Signal
Estimated market salary
₹59-106 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
We’re hiring for a Staff/Principal High-Speed Analog/Mixed-Signal Front-End Design Engineer with 10–12+ years of relevant experience to work on next-generation optical transceivers supporting 112–224 Gb/s data rates.
The role will focus on photonic modulator drivers and high-speed TX front ends, together with TIA, CTLE, high-speed slicers and equalization/analog DSP techniques in the RX path. The role will also involve high-speed custom digital logic, including high-frequency clocking, serializers/deserializers, pipeline logic, dynamic/custom logic and timing-critical datapath circuits.
We’re looking for strong transistor-level CMOS design expertise with a focus on very high 3-dB bandwidth, low noise, low jitter, good linearity, robust timing and power-efficient operation in advanced CMOS technologies.
Qualifications
B.E./B.Tech, M.E./M.Tech or PhD in Electrical/Electronics Engineering, Microelectronics, VLSI or a related field.
10–12+ years of hands-on analog/mixed-signal IC design experience, ideally in high-speed SerDes, optical transceivers or wireline interfaces.
Strong experience in TIA, CTLE, high-speed amplifiers, slicers/comparators, TX drivers, clocking and custom high-speed digital circuits.
Strong understanding of noise, jitter, bandwidth, stability, equalization, signal integrity and high-speed clock/data timing.
Experience with advanced CMOS/FinFET technologies, schematic-to-layout interaction, parasitic extraction and post-layout verification.
Hands-on experience with Cadence Virtuoso/Spectre and high-speed analog/mixed-signal simulation flows.
Experience with silicon photonics, photonic modulators, photodiodes, SerDes or optical link design would be highly desirable.
Ability to take ownership from architecture and specification definition through transistor-level design, verification, layout support and silicon debug.
Strong technical communication skills and ability to work effectively across analog, digital, photonics, layout, package and system teams.
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The role will focus on photonic modulator drivers and high-speed TX front ends, together with TIA, CTLE, high-speed slicers and equalization/analog DSP techniques in the RX path. The role will also involve high-speed custom digital logic, including high-frequency clocking, serializers/deserializers, pipeline logic, dynamic/custom logic and timing-critical datapath circuits.
We’re looking for strong transistor-level CMOS design expertise with a focus on very high 3-dB bandwidth, low noise, low jitter, good linearity, robust timing and power-efficient operation in advanced CMOS technologies.
Qualifications
B.E./B.Tech, M.E./M.Tech or PhD in Electrical/Electronics Engineering, Microelectronics, VLSI or a related field.
10–12+ years of hands-on analog/mixed-signal IC design experience, ideally in high-speed SerDes, optical transceivers or wireline interfaces.
Strong experience in TIA, CTLE, high-speed amplifiers, slicers/comparators, TX drivers, clocking and custom high-speed digital circuits.
Strong understanding of noise, jitter, bandwidth, stability, equalization, signal integrity and high-speed clock/data timing.
Experience with advanced CMOS/FinFET technologies, schematic-to-layout interaction, parasitic extraction and post-layout verification.
Hands-on experience with Cadence Virtuoso/Spectre and high-speed analog/mixed-signal simulation flows.
Experience with silicon photonics, photonic modulators, photodiodes, SerDes or optical link design would be highly desirable.
Ability to take ownership from architecture and specification definition through transistor-level design, verification, layout support and silicon debug.
Strong technical communication skills and ability to work effectively across analog, digital, photonics, layout, package and system teams.
Show more Show less