XU
Staff CAD Engineer
Accepting applicationsXoriant US Staffing · Austin, TX
Contract Mid_senior ASICCadenceMentorRTLSoC
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Staff CAD Engineer
6+ Months Contract
Only W2
Description
• Execute the technical roadmap for CAD engineering and contribute to the design of next-generation tools, flows, and methodologies that enable power-efficient, scalable GPU and SoC designs across advanced process nodes.
• Help deliver robust automation, debug complex tool and flow issues, and help drive consistent adoption of best practices across design organizations.
• Support low-power design enablement at scale, contribute to methodologies for power analysis, optimization, verification, and signoff while aligning on close integration with RTL, physical design, and DTCO strategies.
• Help advancing cross-functional and external collaboration, partnering with internal engineering teams and external vendors to leverage tool capabilities, resolve systemic design challenges, and accelerate technology readiness.
• Take initiatives on moderate-to-complex projects, advance best practices by maintaining technical documentation and staying ahead of emerging GPU and verification technologies.
Requirements
• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
• 6+ years of hands-on experience with hands-on experience CAD, design methodology, or design enablement for GPU, CPU, or other complex SoC programs.
• Working knowledge and experience with low-power tools and methodologies, including RTL and gate-level power analysis, optimization, and signoff flows (e.g., PrimePower, PowerArtist, Empower, Joules, RTL-Architect, or equivalent).
• Solid understanding of the end-to-end ASIC and design flow, including RTL, verification, synthesis, physical design, timing, power, EMIR, DTCO considerations.
• Solid experience with CAD tools for simulation, synthesis, linting, and verification (e.g., Synopsys, Cadence, Mentor Graphics).
• Working knowledge and hands-on experience with EMIR tools and methodologies, including transistor, gate, and package level analysis (e.g. Redhawk, Totem, Voltus)
• Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
• Excellent collaboration and communication skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment.
Show more Show less
6+ Months Contract
Only W2
Description
• Execute the technical roadmap for CAD engineering and contribute to the design of next-generation tools, flows, and methodologies that enable power-efficient, scalable GPU and SoC designs across advanced process nodes.
• Help deliver robust automation, debug complex tool and flow issues, and help drive consistent adoption of best practices across design organizations.
• Support low-power design enablement at scale, contribute to methodologies for power analysis, optimization, verification, and signoff while aligning on close integration with RTL, physical design, and DTCO strategies.
• Help advancing cross-functional and external collaboration, partnering with internal engineering teams and external vendors to leverage tool capabilities, resolve systemic design challenges, and accelerate technology readiness.
• Take initiatives on moderate-to-complex projects, advance best practices by maintaining technical documentation and staying ahead of emerging GPU and verification technologies.
Requirements
• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
• 6+ years of hands-on experience with hands-on experience CAD, design methodology, or design enablement for GPU, CPU, or other complex SoC programs.
• Working knowledge and experience with low-power tools and methodologies, including RTL and gate-level power analysis, optimization, and signoff flows (e.g., PrimePower, PowerArtist, Empower, Joules, RTL-Architect, or equivalent).
• Solid understanding of the end-to-end ASIC and design flow, including RTL, verification, synthesis, physical design, timing, power, EMIR, DTCO considerations.
• Solid experience with CAD tools for simulation, synthesis, linting, and verification (e.g., Synopsys, Cadence, Mentor Graphics).
• Working knowledge and hands-on experience with EMIR tools and methodologies, including transistor, gate, and package level analysis (e.g. Redhawk, Totem, Voltus)
• Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
• Excellent collaboration and communication skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment.
Show more Show less