T
STA (Static Timing Analysis)
Accepting applicationsTaggd · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceInnovusRTLSynopsys
Posted
5d ago
Category
Eda
Experience
Mid_senior
Country
India
Hiring for: A leading global IT Services & Consulting firm (Top 5 in India)
Job Title: STA (Static Timing Analysis)
Location: Bangalore
Notice Period: Immediate to 60 days
Experience: 4.5 years to 7 years
Key Responsibilities
PNR Implementation: Lead the place-and-route (PNR) implementation process, including floor planning, placement, clock tree synthesis (CTS), and post-route optimisation for advanced technology nodes (e.g., 7nm, 5nm, 4nm)
Signoff Closure: Ensure signoff closure for timing (STA), power (PDN), and physical verification (DRC/LVS) across multiple corners and modes
Power Integrity Analysis: Perform power grid analysis and optimization to meet power delivery requirements.
Collaboration: Work closely with cross-functional teams, including RTL, STA, and CAD engineers, to resolve design issues and meet performance, power, and area (PPA) tar
Tool Expertise: Utilize industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, and Synopsys PrimeTime for implementation and verification tasks
Documentation: Prepare detailed documentation for design decisions, methodologies, and tool flows.
Required Qualifications
Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or a related field.
Experience: Minimum of 4.5 years of hands-on experience in physical design, with a strong background in PNR, STA, and PDN
Technical Skills:
Proficiency in PNR flows for advanced technology nodes (7nm and below).
Strong understanding of timing analysis (STA), power analysis (PDN), and physical verification (DRC/LVS).
Experience with power grid analysis and optimization.
Familiarity with EDA tools such as Cadence Innovus, Synopsys ICC2, and Synopsys PrimeTime.
Soft Skills:
Excellent analytical and problem-solving abilities.
Strong communication and teamwork skills.
Ability to work in a fast-paced and dynamic environment.
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Job Title: STA (Static Timing Analysis)
Location: Bangalore
Notice Period: Immediate to 60 days
Experience: 4.5 years to 7 years
Key Responsibilities
PNR Implementation: Lead the place-and-route (PNR) implementation process, including floor planning, placement, clock tree synthesis (CTS), and post-route optimisation for advanced technology nodes (e.g., 7nm, 5nm, 4nm)
Signoff Closure: Ensure signoff closure for timing (STA), power (PDN), and physical verification (DRC/LVS) across multiple corners and modes
Power Integrity Analysis: Perform power grid analysis and optimization to meet power delivery requirements.
Collaboration: Work closely with cross-functional teams, including RTL, STA, and CAD engineers, to resolve design issues and meet performance, power, and area (PPA) tar
Tool Expertise: Utilize industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, and Synopsys PrimeTime for implementation and verification tasks
Documentation: Prepare detailed documentation for design decisions, methodologies, and tool flows.
Required Qualifications
Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or a related field.
Experience: Minimum of 4.5 years of hands-on experience in physical design, with a strong background in PNR, STA, and PDN
Technical Skills:
Proficiency in PNR flows for advanced technology nodes (7nm and below).
Strong understanding of timing analysis (STA), power analysis (PDN), and physical verification (DRC/LVS).
Experience with power grid analysis and optimization.
Familiarity with EDA tools such as Cadence Innovus, Synopsys ICC2, and Synopsys PrimeTime.
Soft Skills:
Excellent analytical and problem-solving abilities.
Strong communication and teamwork skills.
Ability to work in a fast-paced and dynamic environment.
Show more Show less