SS
Sr. FPGA Design Engineer
Accepting applicationsSoloPoint Solutions · Santa Clara, CA
Full-Time Mid_senior FPGAI2CPCIePythonRTL
Posted
21h ago
Category
Design
Experience
Mid_senior
Country
United States
Key Responsibilities:
RTL Architecture & Design: Design and implement RTL in Verilog/SystemVerilog targeting the Xilinx XC7Axx FPGA.
PCIe Endpoint & Custom CSR: Integrate Xilinx PCIe Endpoint IP and design custom Control and Status Registers (CSR) / glue logic to manage hardware operations over PCIe.
I2C & Muxing Infrastructure: Develop and instantiate parallel I2C master controllers and build a muxing matrix to route I2C communications across 32 OSFP slave cages.
Transceiver Management (CMIS): Implement hardware logic to perform high-frequency reads/writes of optical telemetry and control data from Common Management Interface Specification (CMIS) registers over I2C.
Peripherals RTL: Design custom RTL modules for LED status/telemetry pipelines and SPI data transfer logic.
Verification & Simulation: Build robust testbenches (SystemVerilog/UVM preferred) to simulate and verify all custom modules, top-level integration, and corner cases.
Hardware Debugging & Protocol Analysis: Perform system-level hardware validation using logic analyzers, oscilloscopes, and Xilinx Vivado ILA to debug PCIe, I2C, and SPI protocol issues.
Synthesis & Timing Closure: Drive synthesis, place-and-route, and timing closure in Xilinx Vivado to achieve optimal target clock frequencies and resource utilization on a compact Artix-7 footprint.
Onsite Collaboration: Work directly with hardware/embedded teams on-site when required for lab bring-up, debugging, and system verification.
Required Qualifications:
Experience: 10+ years of industry experience in FPGA RTL design, implementation, and verification (preferably with deep expertise in the Xilinx ecosystem).
Toolchain Mastery: Deep proficiency with Xilinx Vivado (Synthesis, Implementation, IP Integrator, ILA/ChipScope, Timing Constraints / XDC).
Protocols & Standards: Hands-on experience with PCIe (Gen1/Gen2), I2C, SPI, and familiarity with CMIS / SFF specifications for optical transceivers.
Bus Topologies: Experience designing custom register spaces, memory-mapped interconnects, and dynamic routing/muxing logic for high-density interfaces (e.g., 32 OSFP cages).
Verification Skills: Demonstrated experience writing self-checking testbenches and automated test environments for block-level and top-level verification.
Timing Closure: Strong track record of achieving timing closure on resource-constrained devices, including multicycle paths, clock domain crossing (CDC), and constraints management.
Lab Debug: Hands-on hardware lab bring-up skills with standard test equipment (logic analyzers, protocol analyzers for PCIe/I2C/SPI).
Location Flexibility: Open to being onsite as needed during critical bring-up and integration phases.
Preferred Qualifications
Prior experience working with high-density optical modules (OSFP, QSFP-DD, QSFP28).
Scripting capability (Python, Tcl, Bash) for Vivado automation and test generation.
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RTL Architecture & Design: Design and implement RTL in Verilog/SystemVerilog targeting the Xilinx XC7Axx FPGA.
PCIe Endpoint & Custom CSR: Integrate Xilinx PCIe Endpoint IP and design custom Control and Status Registers (CSR) / glue logic to manage hardware operations over PCIe.
I2C & Muxing Infrastructure: Develop and instantiate parallel I2C master controllers and build a muxing matrix to route I2C communications across 32 OSFP slave cages.
Transceiver Management (CMIS): Implement hardware logic to perform high-frequency reads/writes of optical telemetry and control data from Common Management Interface Specification (CMIS) registers over I2C.
Peripherals RTL: Design custom RTL modules for LED status/telemetry pipelines and SPI data transfer logic.
Verification & Simulation: Build robust testbenches (SystemVerilog/UVM preferred) to simulate and verify all custom modules, top-level integration, and corner cases.
Hardware Debugging & Protocol Analysis: Perform system-level hardware validation using logic analyzers, oscilloscopes, and Xilinx Vivado ILA to debug PCIe, I2C, and SPI protocol issues.
Synthesis & Timing Closure: Drive synthesis, place-and-route, and timing closure in Xilinx Vivado to achieve optimal target clock frequencies and resource utilization on a compact Artix-7 footprint.
Onsite Collaboration: Work directly with hardware/embedded teams on-site when required for lab bring-up, debugging, and system verification.
Required Qualifications:
Experience: 10+ years of industry experience in FPGA RTL design, implementation, and verification (preferably with deep expertise in the Xilinx ecosystem).
Toolchain Mastery: Deep proficiency with Xilinx Vivado (Synthesis, Implementation, IP Integrator, ILA/ChipScope, Timing Constraints / XDC).
Protocols & Standards: Hands-on experience with PCIe (Gen1/Gen2), I2C, SPI, and familiarity with CMIS / SFF specifications for optical transceivers.
Bus Topologies: Experience designing custom register spaces, memory-mapped interconnects, and dynamic routing/muxing logic for high-density interfaces (e.g., 32 OSFP cages).
Verification Skills: Demonstrated experience writing self-checking testbenches and automated test environments for block-level and top-level verification.
Timing Closure: Strong track record of achieving timing closure on resource-constrained devices, including multicycle paths, clock domain crossing (CDC), and constraints management.
Lab Debug: Hands-on hardware lab bring-up skills with standard test equipment (logic analyzers, protocol analyzers for PCIe/I2C/SPI).
Location Flexibility: Open to being onsite as needed during critical bring-up and integration phases.
Preferred Qualifications
Prior experience working with high-density optical modules (OSFP, QSFP-DD, QSFP28).
Scripting capability (Python, Tcl, Bash) for Vivado automation and test generation.
Show more Show less