WG
Sr. ASIC Design Engineer
Accepting applicationsWorkGenius Group · San Jose, CA
Contract Associate ASICC++DFTFPGAGenus
Posted
6d ago
Category
Design
Experience
Associate
Country
United States
Title: Sr. ASIC Design Engineer
Industry: Silicon Engineering
Location: San Jose, CA
Duration: Temp to Perm
Responsibilities
Translate system requirements into detailed digital design specifications and develop optimized RTL using Verilog/SystemVerilog.
Collaborate with analog, photonics, firmware, and systems engineers on algorithms, interfaces, and control logic.
Build models, testbenches, and verification environments for digital and mixed-signal blocks.
Provide timing, clocking, floorplanning, implementation, and timing-closure guidance to physical-design teams.
Support ASIC flow improvements, silicon bring-up, debug, characterization, and Python-based automation for high-speed interconnect or SerDes-related development.
Requirements
BS in Electrical Engineering, Computer Engineering, or a related field, with 5+ years of ASIC design experience; an MS is preferred.
Strong Verilog/SystemVerilog skills across RTL design and verification, with experience using simulation tools such as VCS, Xcelium, or Questa.
Proficiency in Python and C/C++, plus working knowledge of ASIC tool flows, timing constraints, and multi-clock-domain design.
Experience with SoC interconnect protocols such as AXI, AHB, or APB; synthesis experience with Genus or Design Compiler is preferred.
Ability to independently own complex technical work from definition through completion; silicon bring-up, mixed-signal IP integration, DFT, SerDes, FPGA, or control-systems experience is preferred.
Skills
ASIC Design
RTL
Verilog
SystemVerilog
ASIC Verification
Python
Timing Closure
SoC Interconnect
Silicon Bring-Up
SerDes
Hourly rate is commensurate with experience and is an estimated range provided by WorkGenius.
ref_id: f74bafa7-7434-49dd-a016-0f9cf7220f35
Show more Show less
Industry: Silicon Engineering
Location: San Jose, CA
Duration: Temp to Perm
Responsibilities
Translate system requirements into detailed digital design specifications and develop optimized RTL using Verilog/SystemVerilog.
Collaborate with analog, photonics, firmware, and systems engineers on algorithms, interfaces, and control logic.
Build models, testbenches, and verification environments for digital and mixed-signal blocks.
Provide timing, clocking, floorplanning, implementation, and timing-closure guidance to physical-design teams.
Support ASIC flow improvements, silicon bring-up, debug, characterization, and Python-based automation for high-speed interconnect or SerDes-related development.
Requirements
BS in Electrical Engineering, Computer Engineering, or a related field, with 5+ years of ASIC design experience; an MS is preferred.
Strong Verilog/SystemVerilog skills across RTL design and verification, with experience using simulation tools such as VCS, Xcelium, or Questa.
Proficiency in Python and C/C++, plus working knowledge of ASIC tool flows, timing constraints, and multi-clock-domain design.
Experience with SoC interconnect protocols such as AXI, AHB, or APB; synthesis experience with Genus or Design Compiler is preferred.
Ability to independently own complex technical work from definition through completion; silicon bring-up, mixed-signal IP integration, DFT, SerDes, FPGA, or control-systems experience is preferred.
Skills
ASIC Design
RTL
Verilog
SystemVerilog
ASIC Verification
Python
Timing Closure
SoC Interconnect
Silicon Bring-Up
SerDes
Hourly rate is commensurate with experience and is an estimated range provided by WorkGenius.
ref_id: f74bafa7-7434-49dd-a016-0f9cf7220f35
Show more Show less