AT
SOC Micro-Architect and RTL Designer
Accepting applicationsAcceler8 Talent · Mountain View, CA
Full-Time Mid_senior AIASICC++DFTPCIe
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
SoC Micro-Architect & RTL Designer
Hybrid – Mountain View, CA | Tuesday–Thursday on-site
$200k+ base + RSUs
I’m working with a well-funded AI semiconductor startup building a new processor architecture specifically for frontier-scale language models.
Rather than adapting a general-purpose GPU, the team is co-designing the silicon and software around the throughput, latency, memory, and interconnect demands of large-model training and inference.
The company is moving its first-generation platform toward tape-out and product delivery, giving engineers the opportunity to influence important architectural and implementation decisions before conventions become fixed.
You’ll work on problems such as:
Translating architectural requirements into production-quality microarchitecture and RTL
Owning blocks or subsystems from specification through sign-off
Developing compute, memory-management, or high-speed-connectivity functionality
Optimizing performance, power, area, and timing
Working across verification, DFT, physical design, architecture, and software
Supporting silicon bring-up and debug
Looking for engineers who have:
5+ years of SoC or ASIC microarchitecture and RTL-design experience
Strong SystemVerilog skills, plus experience with Python or C/C++
Experience taking complex designs toward production silicon
Hands-on knowledge of synthesis, lint, CDC, and equivalence checking
Experience delivering high-performance compute, memory, or connectivity designs
A clear understanding of how RTL decisions affect timing, power, area, and physical implementation.
Nice to have:
PCIe, HBM, DMA, or die-to-die subsystem experience
CPU, GPU, or machine-learning accelerator experience
Emulation, silicon bring-up, or post-silicon debug experience
Ownership of a complete subsystem through tape-out.
The strongest candidates will be able to explain what they personally architected, implemented, closed, and delivered on previous silicon programmes.
Candidates must be authorized to work in the United States and able to work from the Mountain View office Tuesday through Thursday.
Worth a confidential chat?
Show more Show less
Hybrid – Mountain View, CA | Tuesday–Thursday on-site
$200k+ base + RSUs
I’m working with a well-funded AI semiconductor startup building a new processor architecture specifically for frontier-scale language models.
Rather than adapting a general-purpose GPU, the team is co-designing the silicon and software around the throughput, latency, memory, and interconnect demands of large-model training and inference.
The company is moving its first-generation platform toward tape-out and product delivery, giving engineers the opportunity to influence important architectural and implementation decisions before conventions become fixed.
You’ll work on problems such as:
Translating architectural requirements into production-quality microarchitecture and RTL
Owning blocks or subsystems from specification through sign-off
Developing compute, memory-management, or high-speed-connectivity functionality
Optimizing performance, power, area, and timing
Working across verification, DFT, physical design, architecture, and software
Supporting silicon bring-up and debug
Looking for engineers who have:
5+ years of SoC or ASIC microarchitecture and RTL-design experience
Strong SystemVerilog skills, plus experience with Python or C/C++
Experience taking complex designs toward production silicon
Hands-on knowledge of synthesis, lint, CDC, and equivalence checking
Experience delivering high-performance compute, memory, or connectivity designs
A clear understanding of how RTL decisions affect timing, power, area, and physical implementation.
Nice to have:
PCIe, HBM, DMA, or die-to-die subsystem experience
CPU, GPU, or machine-learning accelerator experience
Emulation, silicon bring-up, or post-silicon debug experience
Ownership of a complete subsystem through tape-out.
The strongest candidates will be able to explain what they personally architected, implemented, closed, and delivered on previous silicon programmes.
Candidates must be authorized to work in the United States and able to work from the Mountain View office Tuesday through Thursday.
Worth a confidential chat?
Show more Show less