SP
Silicon Patterns - Senior RTL design careers
Accepting applicationsSilicon Patterns · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICPCIeRTLSoCSystemVerilog
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
🚀 Hiring: Senior RTL Design Engineers – PCIe to join our #Semiconductor and #Embedded teams at #SiliconPatterns in
📍#Bengaluru, Coimbatore and #Hyderabad
🫧No. Of positions: Multiple
💼 Experience: 8 - 15 Years
🎁CTC range: INR 40 - 90 LPA
🖲️Interested candidates with below skills can apply i
📯Key Skills:
#RTL Design Engineer with strong expertise in #PCIe and #ASIC/ #SoC development plus the below skills..
✅ Verilog/SystemVerilog
✅PCIe Gen3/Gen4/Gen5
✅ PCIe Controller/IP & LTSSM
✅TLP/DLLP, Flow Control & Error Handling
✅CDC/RDC, Lint & Synthesis
✅RTL Simulation & Debugging
✅ASIC/SoC Design & PPA Optimization
✔️Good to have:
✅PCIe Gen6, CXL, AXI, DMA, Formal Verification and Silicon Bring-up.
If you are passionate about high-performance semiconductor design and looking for your next opportunity, we'd love to hear from you.
#Semiconductor #VLSI #SystemVerilog #ChipDesign #EngineeringJobs
Show more Show less
📍#Bengaluru, Coimbatore and #Hyderabad
🫧No. Of positions: Multiple
💼 Experience: 8 - 15 Years
🎁CTC range: INR 40 - 90 LPA
🖲️Interested candidates with below skills can apply i
📯Key Skills:
#RTL Design Engineer with strong expertise in #PCIe and #ASIC/ #SoC development plus the below skills..
✅ Verilog/SystemVerilog
✅PCIe Gen3/Gen4/Gen5
✅ PCIe Controller/IP & LTSSM
✅TLP/DLLP, Flow Control & Error Handling
✅CDC/RDC, Lint & Synthesis
✅RTL Simulation & Debugging
✅ASIC/SoC Design & PPA Optimization
✔️Good to have:
✅PCIe Gen6, CXL, AXI, DMA, Formal Verification and Silicon Bring-up.
If you are passionate about high-performance semiconductor design and looking for your next opportunity, we'd love to hear from you.
#Semiconductor #VLSI #SystemVerilog #ChipDesign #EngineeringJobs
Show more Show less