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Senior Synthesis & Place & Route (P&R) Engineer – MRAM Subsystems
Accepting applicationsNumem · Mesa, AZ
Full-Time Mid_senior CadenceCalibreDFTGenusInnovus
Posted
2d ago
Category
Eda
Experience
Mid_senior
Country
United States
Job Description: Senior Synthesis & Place & Route (P&R) Engineer – MRAM Subsystems
Location: Mesa, AZ
Department: Physical Design & Emerging Memory Engineering
Job Type: Full-Time
About the Role
We are seeking an experienced Synthesis & Place & Route (P&R) Design Engineer specializing in emerging non-volatile memory (NVM) architectures to join our next-generation MRAM Design Team. In this role, you will lead the digital physical implementation (RTL to GDSII) for embedded MRAM (eMRAM) controllers, peripheral digital logic, write/read timing control, and integrated SoC memory subsystems (STT-MRAM / SOT-MRAM).
You will bridge the gap between RTL logic design, high-density MRAM macro integration, and foundry physical implementation playing a vital role in balancing Power, Performance, Area (PPA), and magnetic/thermal integrity at advanced process nodes.
Key Responsibilities
1. Synthesis, Constraints & ECC Logic
· Lead synthesis and DFT insertion (scan, MBIST/LBIST) for complex digital memory controllers, built-in self-repair (BISR) logic, and specialized Error-Correcting Code (ECC) engines tailored for MRAM reliability.
· Develop and maintain complex Multi-Corner Multi-Mode (MCMM) timing constraints (SDC) for high-speed read/write interfaces across extreme temperature and voltage ranges.
· Optimize synthesized netlists to take advantage of MRAM’s non-volatile nature for instant-on capabilities and ultra-low leakage power targets.
2. Floor planning & P&R with MRAM Integration
· Work closely with custom layout teams to build full chip floor plan comprehending hard macro placement, reset and timing constraints and package design rules.
· Execute macro placement and floor planning for dense MRAM arrays, handling unique Backend-of-Line (BEOL) layer stack constraints caused by Magnetic Tunnel Junction (MTJ) module integration.
· Construct robust Power Delivery Networks (PDN) capable of handling transient current surges and high write-peak currents required during high-speed switching operations
· Develop and implement power domain adhering to power domain crossing rules
· Drive end-to-end Place & Route tasks, including custom clock tree synthesis (CTS) designed to minimize jitter and skew across dense MRAM macro boundaries.
3. Power Integrity & Sign-off STA
· Perform rigorous static and dynamic IR-drop analysis to prevent voltage droop during simultaneous MRAM array write operations.
· Execute Static Timing Analysis (STA) and timing closure across standard and specialized process-voltage-temperature (PVT) corners.
· Implement state-retention, power-gating, and multi-voltage methodologies using UPF/CPF to leverage MRAM’s zero-standby-power advantage.
4. Physical Verification & Foundry Interface
· Drive physical verification (DRC, LVS, ERC, Antenna) to full sign-off, ensuring compliance with specialized eMRAM foundry design rules and BEOL rule sets.
· Collaborate with foundry CAD teams and circuit designers to resolve macro interface, seal-ring, and layout-dependent effects (LDE).
· Build and maintain scalable Tcl/Python scripts to refine automated physical design and sign-off flows.
Required Qualifications
· Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
· Experience: 7+ years of hands-on physical design experience from logical synthesis to GDSII sign-off.
· Tool Proficiency:
o Synthesis & DFT: Synopsys Design/Fusion Compiler or Cadence Genus; Tessent / Synopsys DFT.
o P&R Implementation: Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
o STA & Power Integrity: Synopsys PrimeTime / RedHawk or Cadence Tempus / Voltus.
o Physical Verification: Siemens Calibre (DRC/LVS) or Synopsys ICV.
· Scripting: Advanced proficiency in Tcl and Python for flow customization and data analysis.
· Demonstrated experience handling complex physical constraints, macro placement, and high-current power grid design.
Preferred Qualifications
· Experience with rule sets spanning multiple nodes in the foundry ecosystem
· Knowledge and experience in package design constraints
· Direct experience with MRAM (STT-MRAM, SOT-MRAM), eMRAM, or other emerging Non-Volatile Memory technologies (ReRAM, PCM).
· Familiarity with BEOL process integration constraints (e.g., MTJ placement between specific metal layers affecting routing tracks).
· Experience implementing low-power architectures leveraging non-volatile memory for fast wake-up / deep sleep states.
· Background in synthesizing and closing timing on heavy mathematical logic such as high-throughput ECC (Reed-Solomon, BCH, LDPC) or security modules (PUF, AES).
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Location: Mesa, AZ
Department: Physical Design & Emerging Memory Engineering
Job Type: Full-Time
About the Role
We are seeking an experienced Synthesis & Place & Route (P&R) Design Engineer specializing in emerging non-volatile memory (NVM) architectures to join our next-generation MRAM Design Team. In this role, you will lead the digital physical implementation (RTL to GDSII) for embedded MRAM (eMRAM) controllers, peripheral digital logic, write/read timing control, and integrated SoC memory subsystems (STT-MRAM / SOT-MRAM).
You will bridge the gap between RTL logic design, high-density MRAM macro integration, and foundry physical implementation playing a vital role in balancing Power, Performance, Area (PPA), and magnetic/thermal integrity at advanced process nodes.
Key Responsibilities
1. Synthesis, Constraints & ECC Logic
· Lead synthesis and DFT insertion (scan, MBIST/LBIST) for complex digital memory controllers, built-in self-repair (BISR) logic, and specialized Error-Correcting Code (ECC) engines tailored for MRAM reliability.
· Develop and maintain complex Multi-Corner Multi-Mode (MCMM) timing constraints (SDC) for high-speed read/write interfaces across extreme temperature and voltage ranges.
· Optimize synthesized netlists to take advantage of MRAM’s non-volatile nature for instant-on capabilities and ultra-low leakage power targets.
2. Floor planning & P&R with MRAM Integration
· Work closely with custom layout teams to build full chip floor plan comprehending hard macro placement, reset and timing constraints and package design rules.
· Execute macro placement and floor planning for dense MRAM arrays, handling unique Backend-of-Line (BEOL) layer stack constraints caused by Magnetic Tunnel Junction (MTJ) module integration.
· Construct robust Power Delivery Networks (PDN) capable of handling transient current surges and high write-peak currents required during high-speed switching operations
· Develop and implement power domain adhering to power domain crossing rules
· Drive end-to-end Place & Route tasks, including custom clock tree synthesis (CTS) designed to minimize jitter and skew across dense MRAM macro boundaries.
3. Power Integrity & Sign-off STA
· Perform rigorous static and dynamic IR-drop analysis to prevent voltage droop during simultaneous MRAM array write operations.
· Execute Static Timing Analysis (STA) and timing closure across standard and specialized process-voltage-temperature (PVT) corners.
· Implement state-retention, power-gating, and multi-voltage methodologies using UPF/CPF to leverage MRAM’s zero-standby-power advantage.
4. Physical Verification & Foundry Interface
· Drive physical verification (DRC, LVS, ERC, Antenna) to full sign-off, ensuring compliance with specialized eMRAM foundry design rules and BEOL rule sets.
· Collaborate with foundry CAD teams and circuit designers to resolve macro interface, seal-ring, and layout-dependent effects (LDE).
· Build and maintain scalable Tcl/Python scripts to refine automated physical design and sign-off flows.
Required Qualifications
· Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
· Experience: 7+ years of hands-on physical design experience from logical synthesis to GDSII sign-off.
· Tool Proficiency:
o Synthesis & DFT: Synopsys Design/Fusion Compiler or Cadence Genus; Tessent / Synopsys DFT.
o P&R Implementation: Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
o STA & Power Integrity: Synopsys PrimeTime / RedHawk or Cadence Tempus / Voltus.
o Physical Verification: Siemens Calibre (DRC/LVS) or Synopsys ICV.
· Scripting: Advanced proficiency in Tcl and Python for flow customization and data analysis.
· Demonstrated experience handling complex physical constraints, macro placement, and high-current power grid design.
Preferred Qualifications
· Experience with rule sets spanning multiple nodes in the foundry ecosystem
· Knowledge and experience in package design constraints
· Direct experience with MRAM (STT-MRAM, SOT-MRAM), eMRAM, or other emerging Non-Volatile Memory technologies (ReRAM, PCM).
· Familiarity with BEOL process integration constraints (e.g., MTJ placement between specific metal layers affecting routing tracks).
· Experience implementing low-power architectures leveraging non-volatile memory for fast wake-up / deep sleep states.
· Background in synthesizing and closing timing on heavy mathematical logic such as high-throughput ECC (Reed-Solomon, BCH, LDPC) or security modules (PUF, AES).
Show more Show less