HT
Senior RTL Design Engineer
Accepting applicationsHighbrow Technology Inc · Mountain View, CA
Full-Time Mid_senior ASICDDREthernetPCIePython
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Senior RTL Design Engineer
We are looking for an experienced Senior RTL Design Engineer to join the team and help deliver innovative silicon solutions for internal platforms and customer programs..
Key Responsibilities:
Design and develop digital logic for internal platform and customer SoC projects.
Create functional specifications and develop micro-architectures for digital IP blocks.
Develop high-quality RTL using Verilog, VHDL, and/or SystemVerilog.
Perform block-level design, simulation, debugging, and optimization.
Collaborate with Design Verification and Physical Design teams to take designs from RTL to GDSII.
Support integration, bring-up, and customer engagements throughout the development lifecycle.
Drive technical excellence and contribute to architecture and design reviews..
Required Qualifications:
8+ years of industry experience in digital IC/SoC design.
Proven experience leading or contributing to complex SoC development projects.
Strong RTL design expertise using VHDL, Verilog, or SystemVerilog.
Solid understanding of digital design fundamentals and synchronous design principles.
Experience working with cross-functional engineering teams throughout the ASIC design flow.
Experience in high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet
Control loop design
Chiplet interconnect architectures
Design automation and scripting using Python
📩 Interested candidates? Please share your updated resume to [email protected]
Show more Show less
We are looking for an experienced Senior RTL Design Engineer to join the team and help deliver innovative silicon solutions for internal platforms and customer programs..
Key Responsibilities:
Design and develop digital logic for internal platform and customer SoC projects.
Create functional specifications and develop micro-architectures for digital IP blocks.
Develop high-quality RTL using Verilog, VHDL, and/or SystemVerilog.
Perform block-level design, simulation, debugging, and optimization.
Collaborate with Design Verification and Physical Design teams to take designs from RTL to GDSII.
Support integration, bring-up, and customer engagements throughout the development lifecycle.
Drive technical excellence and contribute to architecture and design reviews..
Required Qualifications:
8+ years of industry experience in digital IC/SoC design.
Proven experience leading or contributing to complex SoC development projects.
Strong RTL design expertise using VHDL, Verilog, or SystemVerilog.
Solid understanding of digital design fundamentals and synchronous design principles.
Experience working with cross-functional engineering teams throughout the ASIC design flow.
Experience in high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet
Control loop design
Chiplet interconnect architectures
Design automation and scripting using Python
📩 Interested candidates? Please share your updated resume to [email protected]
Show more Show less