ED
Senior Physical Design Architect
Accepting applicationsEximietas Design · Hyderabad, Telangana, India
Full-Time Mid_senior RTLVLSIanalog
Estimated market salary
₹59-105 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
🚀 Eximietas is Hiring – Senior Physical Design Engineers, Leads & Architects.
Experience: 6 to 20+ Years
🔎 Open Roles
✔ PD CAD
✔ PD Power
✔ Physical Verification
✔ PD EMIR
📍Locations:
India: Bengaluru, Hyderabad, Pune & Ahmedabad.
San Jose (Bay Area), USA
Austin, USA
Eligibility (USA): U.S. Permanent Residents (Green Card holders).
Qualifications:
Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI Engineering
Minimum 6 years of experience in Physical Design with mainstream P&R tools
Roles & Responsibilities:
Work on 10nm / 7nm / 5nm and below technology node designs
Solve critical customer design challenges across performance, power, and area
Develop and optimize flows/methodologies for placement, CTS, and routing
Provide training, deployment support, and technical guidance to customers
Required Technical & Professional Expertise:
Strong experience in place & route flows (placement, CTS, routing, timing optimization)
Knowledge of hierarchical designs and/or low-power implementation
Experience in Synthesis and collaboration with RTL/implementation teams
Expertise in Floorplanning (macro placement, padring, power grid, custom analog routing)
Strong understanding of STA, constraints, parasitic extraction & sign-off
Awareness of Physical Verification (DRC/LVS/DFM, chip finishing)
📨 Interested candidates, please share your resumes: maruthiprasad.e@eximietas.design
🤝 Referrals are highly appreciated....! please feel free to forward this within your network...!
Best regards,
Maruthy Prasaad
Associate VLSI Manager - Talent Acquisition | Visakhapatnam
Eximietas Design
maruthiprasad.e@eximietas.design
+91 8088969910.
Show more Show less
Experience: 6 to 20+ Years
🔎 Open Roles
✔ PD CAD
✔ PD Power
✔ Physical Verification
✔ PD EMIR
📍Locations:
India: Bengaluru, Hyderabad, Pune & Ahmedabad.
San Jose (Bay Area), USA
Austin, USA
Eligibility (USA): U.S. Permanent Residents (Green Card holders).
Qualifications:
Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI Engineering
Minimum 6 years of experience in Physical Design with mainstream P&R tools
Roles & Responsibilities:
Work on 10nm / 7nm / 5nm and below technology node designs
Solve critical customer design challenges across performance, power, and area
Develop and optimize flows/methodologies for placement, CTS, and routing
Provide training, deployment support, and technical guidance to customers
Required Technical & Professional Expertise:
Strong experience in place & route flows (placement, CTS, routing, timing optimization)
Knowledge of hierarchical designs and/or low-power implementation
Experience in Synthesis and collaboration with RTL/implementation teams
Expertise in Floorplanning (macro placement, padring, power grid, custom analog routing)
Strong understanding of STA, constraints, parasitic extraction & sign-off
Awareness of Physical Verification (DRC/LVS/DFM, chip finishing)
📨 Interested candidates, please share your resumes: maruthiprasad.e@eximietas.design
🤝 Referrals are highly appreciated....! please feel free to forward this within your network...!
Best regards,
Maruthy Prasaad
Associate VLSI Manager - Talent Acquisition | Visakhapatnam
Eximietas Design
maruthiprasad.e@eximietas.design
+91 8088969910.
Show more Show less