TT
Senior MBIST Engineer
Accepting applicationsThunderhawk Technology Partners · United States
Contract Mid_senior ATPGDFTPerlPythonRTL
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Position Overview
We are seeking a highly experienced Senior MBIST Engineer to join our SoC Design-for-Test (DFT) team. The ideal candidate will have strong hands-on experience with Synopsys MBIST (SMS5/SMS6) and be capable of independently owning the complete MBIST flow from insertion and integration through verification, simulation, pattern generation, debug, and silicon bring-up.
This is a hands-on individual contributor role requiring deep MBIST expertise and strong debugging skills across RTL, gate-level simulation, and silicon environments.
Key Responsibilities
Perform MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST at the top-level SoC environment.
Develop, execute, and debug MBIST simulations using Synopsys VCS.
Perform RTL, no-delay gate-level, and with-delay/timing-aware simulations.
Generate and validate MBIST test patterns using VecGen.
Debug RTL, simulation, MBIST integration, and memory-related issues.
Support silicon bring-up, characterization, and post-silicon debug.
Troubleshoot MBIST failures and memory-related issues and perform root-cause analysis.
Work closely with DFT, RTL, Physical Design, and Product Engineering teams.
Drive issues independently from identification through resolution.
Document MBIST implementation flows, debug methodology, and findings.
Required Qualifications
8+ years of hands-on DFT experience, with significant MBIST experience.
Strong experience with Synopsys MBIST (SMS), preferably SMS5 and/or SMS6.
Strong proficiency with Synopsys VCS for MBIST verification and simulation.
Deep understanding of the complete MBIST flow, including:
MBIST insertion
Top-level integration
Verification
Pattern generation using VecGen
Diagnostics
Simulation and debug
Strong knowledge of MBIST algorithms, including March algorithms.
Experience with memory repair schemes such as BIRA/BISR, redundancy analysis, and spare row/column allocation.
Experience running and debugging no-delay and with-delay simulations.
Experience with silicon bring-up and post-silicon debug.
Strong RTL, simulation, and MBIST debugging/root-cause analysis skills.
Experience working with large, complex SoC designs containing multiple memory instances.
Familiarity with Verilog/SystemVerilog and standard DFT methodologies.
Ability to work independently with minimal supervision.
Preferred Qualifications
Experience with advanced SoC DFT integration.
Familiarity with ATPG and scan insertion flows.
Scripting experience with Tcl, Perl, or Python.
Experience working in fast-paced semiconductor product development environments.
Key Skills
Must Have:
Synopsys MBIST | SMS5/SMS6 | MBIST Insertion | VCS | VecGen | MBIST Verification | MBIST Diagnostics | March Algorithms | BIRA/BISR | Memory Repair | No-Delay Simulation | With-Delay Simulation | Silicon Bring-Up | Post-Silicon Debug | SoC DFT
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We are seeking a highly experienced Senior MBIST Engineer to join our SoC Design-for-Test (DFT) team. The ideal candidate will have strong hands-on experience with Synopsys MBIST (SMS5/SMS6) and be capable of independently owning the complete MBIST flow from insertion and integration through verification, simulation, pattern generation, debug, and silicon bring-up.
This is a hands-on individual contributor role requiring deep MBIST expertise and strong debugging skills across RTL, gate-level simulation, and silicon environments.
Key Responsibilities
Perform MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST at the top-level SoC environment.
Develop, execute, and debug MBIST simulations using Synopsys VCS.
Perform RTL, no-delay gate-level, and with-delay/timing-aware simulations.
Generate and validate MBIST test patterns using VecGen.
Debug RTL, simulation, MBIST integration, and memory-related issues.
Support silicon bring-up, characterization, and post-silicon debug.
Troubleshoot MBIST failures and memory-related issues and perform root-cause analysis.
Work closely with DFT, RTL, Physical Design, and Product Engineering teams.
Drive issues independently from identification through resolution.
Document MBIST implementation flows, debug methodology, and findings.
Required Qualifications
8+ years of hands-on DFT experience, with significant MBIST experience.
Strong experience with Synopsys MBIST (SMS), preferably SMS5 and/or SMS6.
Strong proficiency with Synopsys VCS for MBIST verification and simulation.
Deep understanding of the complete MBIST flow, including:
MBIST insertion
Top-level integration
Verification
Pattern generation using VecGen
Diagnostics
Simulation and debug
Strong knowledge of MBIST algorithms, including March algorithms.
Experience with memory repair schemes such as BIRA/BISR, redundancy analysis, and spare row/column allocation.
Experience running and debugging no-delay and with-delay simulations.
Experience with silicon bring-up and post-silicon debug.
Strong RTL, simulation, and MBIST debugging/root-cause analysis skills.
Experience working with large, complex SoC designs containing multiple memory instances.
Familiarity with Verilog/SystemVerilog and standard DFT methodologies.
Ability to work independently with minimal supervision.
Preferred Qualifications
Experience with advanced SoC DFT integration.
Familiarity with ATPG and scan insertion flows.
Scripting experience with Tcl, Perl, or Python.
Experience working in fast-paced semiconductor product development environments.
Key Skills
Must Have:
Synopsys MBIST | SMS5/SMS6 | MBIST Insertion | VCS | VecGen | MBIST Verification | MBIST Diagnostics | March Algorithms | BIRA/BISR | Memory Repair | No-Delay Simulation | With-Delay Simulation | Silicon Bring-Up | Post-Silicon Debug | SoC DFT
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