LT
Senior Analog Layout Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Hyderabad, Telangana, India
Full-Time Mid_senior AnalogCMOSCadenceFinFETPython
Estimated market salary
₹46-83 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
22h ago
Category
Design
Experience
Mid_senior
Country
India
Senior Analog Layout Engineer
Location: Hyderabad
Experience: 4–8 Years
Role Overview
We are looking for a Senior Analog Layout Engineer with strong hands-on experience in custom/analog IC layout. The ideal candidate will be responsible for delivering high-quality layouts for complex analog and mixed-signal blocks while working closely with circuit designers to achieve performance, matching, reliability, and area objectives.
Key Responsibilities
Develop custom analog and mixed-signal layouts from schematic/netlist to physical database.
Work on layout of analog blocks such as amplifiers, bandgaps, LDOs, ADC/DAC blocks, PLLs, references, and bias circuits.
Apply advanced layout techniques including matching, common-centroid, interdigitation, shielding, guard rings, and dummy structures.
Perform DRC, LVS, ERC and PEX and resolve layout-related issues.
Collaborate closely with Analog Design, Circuit Design, Verification and Physical Design teams.
Optimize layout for area, parasitics, matching, noise and overall circuit performance.
Analyze and address post-layout simulation and extraction-related issues.
Support top-level/custom block integration and physical verification closure.
Contribute to layout methodology, automation and flow improvements.
Required Skills
4–8 years of relevant experience in Analog/Custom IC Layout.
Strong hands-on experience with Cadence Virtuoso.
Good understanding of CMOS analog layout techniques and advanced matching concepts.
Experience with DRC, LVS, ERC and PEX.
Strong understanding of device physics, parasitics and layout-dependent effects.
Experience with deep-submicron/advanced-node technologies is preferred.
Good exposure to analog/mixed-signal IC design flows.
Ability to independently own blocks from layout initiation through signoff.
Strong debugging and problem-solving skills.
Preferred
Experience with high-performance analog, mixed-signal, PMIC, SerDes, PLL or data-converter layouts.
Exposure to FinFET/GAA or advanced CMOS processes.
Experience with EM/IR, reliability and post-layout simulation.
Scripting/automation experience using SKILL, Tcl or Python is a plus.
Strong communication and cross-functional collaboration skills.
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Location: Hyderabad
Experience: 4–8 Years
Role Overview
We are looking for a Senior Analog Layout Engineer with strong hands-on experience in custom/analog IC layout. The ideal candidate will be responsible for delivering high-quality layouts for complex analog and mixed-signal blocks while working closely with circuit designers to achieve performance, matching, reliability, and area objectives.
Key Responsibilities
Develop custom analog and mixed-signal layouts from schematic/netlist to physical database.
Work on layout of analog blocks such as amplifiers, bandgaps, LDOs, ADC/DAC blocks, PLLs, references, and bias circuits.
Apply advanced layout techniques including matching, common-centroid, interdigitation, shielding, guard rings, and dummy structures.
Perform DRC, LVS, ERC and PEX and resolve layout-related issues.
Collaborate closely with Analog Design, Circuit Design, Verification and Physical Design teams.
Optimize layout for area, parasitics, matching, noise and overall circuit performance.
Analyze and address post-layout simulation and extraction-related issues.
Support top-level/custom block integration and physical verification closure.
Contribute to layout methodology, automation and flow improvements.
Required Skills
4–8 years of relevant experience in Analog/Custom IC Layout.
Strong hands-on experience with Cadence Virtuoso.
Good understanding of CMOS analog layout techniques and advanced matching concepts.
Experience with DRC, LVS, ERC and PEX.
Strong understanding of device physics, parasitics and layout-dependent effects.
Experience with deep-submicron/advanced-node technologies is preferred.
Good exposure to analog/mixed-signal IC design flows.
Ability to independently own blocks from layout initiation through signoff.
Strong debugging and problem-solving skills.
Preferred
Experience with high-performance analog, mixed-signal, PMIC, SerDes, PLL or data-converter layouts.
Exposure to FinFET/GAA or advanced CMOS processes.
Experience with EM/IR, reliability and post-layout simulation.
Scripting/automation experience using SKILL, Tcl or Python is a plus.
Strong communication and cross-functional collaboration skills.
Show more Show less