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RTL Design Engineer ( Lead / Senior )
Accepting applicationsMosChip® · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICRTLSoCVerilog
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
Job Description:
Experience Level: 6 - 12 Years
Location: Bangalore / Hyderabad
Role: Senior / Lead
Work Mode: Work from office ( 5 days a week )
Required Skills
Experience in Logic design / RTL coding is a must.
Experience in SoC design and integration for complex SoCs is a must.
Experience in Verilog/System-Verilog is a must.
Experience in multi-clock designs and asynchronous interfaces is a must.
Experience in using the tools in ASIC development such as Lint and CDC.
Experience in Synthesis / Understanding of timing concepts is a plus.
Experience in ECO fixes and formal verification.
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
Excellent oral and written communication skills.
Proactive, creative, curious, motivated to learn and contribute, with good collaboration skills
Show more Show less
Experience Level: 6 - 12 Years
Location: Bangalore / Hyderabad
Role: Senior / Lead
Work Mode: Work from office ( 5 days a week )
Required Skills
Experience in Logic design / RTL coding is a must.
Experience in SoC design and integration for complex SoCs is a must.
Experience in Verilog/System-Verilog is a must.
Experience in multi-clock designs and asynchronous interfaces is a must.
Experience in using the tools in ASIC development such as Lint and CDC.
Experience in Synthesis / Understanding of timing concepts is a plus.
Experience in ECO fixes and formal verification.
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
Excellent oral and written communication skills.
Proactive, creative, curious, motivated to learn and contribute, with good collaboration skills
Show more Show less