NS
R-10066168 Physical Design Methodology Lead
Accepting applicationsNXP Semiconductors · Austin, TX
Full-Time Mid_senior AIASICCadenceDFTPerl
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Role Overview
We are seeking a senior-level Flow and Methodology Engineer to lead backend design automation for advanced process node SoC and ASIC implementation. This role focuses on enabling robust, scalable, and production-ready RTL-to-GDS flows across synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, power grid implementation, extraction, physical verification, and signoff closure. The ideal candidate will combine deep technical expertise in physical design methodology with the ability to drive initiatives from concept definition through validation, deployment, and sustained production support.
Key Responsibilities
Own, develop, and continuously improve backend RTL-to-GDS implementation flows for advanced process nodes, with emphasis on quality of results, scalability, runtime, and designer productivity.
Drive methodology development across place and route, CTS, timing closure, congestion analysis, ECO implementation, power grid design, IR/EM analysis, extraction, and signoff readiness.
Partner with design, architecture, DFT, verification, timing, low-power, package, foundry, and signoff teams to ensure flows meet tapeout requirements for complex SoC and IP programs.
Lead initiatives from concept and feasibility assessment through prototype development, benchmarking, validation, documentation, deployment, training, and production support.
Establish repeatable best practices, reference flows, automation frameworks, dashboards, and metrics to improve PPA, reduce turnaround time, and improve predictability across projects.
Work closely with EDA vendors to evaluate, enable, and adopt the latest technologies in physical implementation, signoff, power integrity, machine learning optimization, and agentic/AI-assisted design automation.
Conduct competitive benchmarking and technology evaluations to identify flow gaps, quantify benefits, and influence vendor roadmaps.
Debug complex flow, tool, constraint, timing, power, congestion, and physical verification issues, and provide expert guidance to design implementation teams.
Promote automation-first thinking through scripting, reusable infrastructure, regression systems, data-driven flow analysis, and intelligent decision support.
Provide deployment support, training, and hands-on technical leadership to ensure new methodologies are adopted effectively across engineering teams.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Typically, 10+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products.
Strong hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification.
Deep understanding of timing signoff, constraints, STA debug, SDC methodology, multi-corner multi-mode closure, setup/hold optimization, and correlation across implementation and signoff tools.
Experience with power grid design, IR drop, EM analysis, low-power implementation, multi-voltage design, UPF-based flows, and power optimization techniques.
Proven ability to improve PPA through methodology innovation, tool tuning, automation, and cross-functional problem solving.
Strong scripting and automation skills using Tcl, Python, Perl, shell scripting, or equivalent technologies.
Experience working with leading EDA platforms from vendors such as Synopsys, Cadence, Siemens EDA, or equivalent tool ecosystems.
Demonstrated ability to influence technical direction, communicate complex topics clearly, and drive cross-team initiatives to closure.
Preferred Qualifications
Experience enabling advanced process nodes and supporting successful tapeouts on complex SoC, CPU, GPU, DSP, networking, automotive, or high-performance digital designs.
Familiarity with AI/ML-driven EDA optimization, design-space exploration, predictive analytics, automated debugging, and agentic workflow concepts.
Experience building production-quality flow infrastructure, regression frameworks, quality dashboards, and data pipelines for design implementation analytics.
Strong vendor engagement experience, including tool evaluation, benchmark definition, issue escalation, roadmap influence, and early technology adoption.
Ability to mentor engineers, define technical standards, and act as a trusted methodology expert across multiple design teams.
What Success Looks Like
Deployment of reliable, production-ready backend implementation flows that improve project execution efficiency and reduce design closure risk.
Measurable improvement in PPA, runtime, convergence predictability, and signoff correlation across advanced-node programs.
Successful evaluation and adoption of next-generation vendor capabilities, including ML/AI-based optimization and agentic automation technologies.
Strong cross-functional adoption of new methodologies through clear documentation, training, support, and continuous feedback loops.
Recognition as a senior technical leader who can translate emerging EDA technologies into practical, scalable, and high-impact design enablement solutions.
NXP Introduction:
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.
For more information, please visit our website https://www.nxp.com
Career Development Opportunities
The future starts here. Bright Minds. Bright Futures.
We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.
We Are NXP! Visit our careers website for more job information.
Commitment At NXP.
We recognize we can be a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.
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We are seeking a senior-level Flow and Methodology Engineer to lead backend design automation for advanced process node SoC and ASIC implementation. This role focuses on enabling robust, scalable, and production-ready RTL-to-GDS flows across synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, power grid implementation, extraction, physical verification, and signoff closure. The ideal candidate will combine deep technical expertise in physical design methodology with the ability to drive initiatives from concept definition through validation, deployment, and sustained production support.
Key Responsibilities
Own, develop, and continuously improve backend RTL-to-GDS implementation flows for advanced process nodes, with emphasis on quality of results, scalability, runtime, and designer productivity.
Drive methodology development across place and route, CTS, timing closure, congestion analysis, ECO implementation, power grid design, IR/EM analysis, extraction, and signoff readiness.
Partner with design, architecture, DFT, verification, timing, low-power, package, foundry, and signoff teams to ensure flows meet tapeout requirements for complex SoC and IP programs.
Lead initiatives from concept and feasibility assessment through prototype development, benchmarking, validation, documentation, deployment, training, and production support.
Establish repeatable best practices, reference flows, automation frameworks, dashboards, and metrics to improve PPA, reduce turnaround time, and improve predictability across projects.
Work closely with EDA vendors to evaluate, enable, and adopt the latest technologies in physical implementation, signoff, power integrity, machine learning optimization, and agentic/AI-assisted design automation.
Conduct competitive benchmarking and technology evaluations to identify flow gaps, quantify benefits, and influence vendor roadmaps.
Debug complex flow, tool, constraint, timing, power, congestion, and physical verification issues, and provide expert guidance to design implementation teams.
Promote automation-first thinking through scripting, reusable infrastructure, regression systems, data-driven flow analysis, and intelligent decision support.
Provide deployment support, training, and hands-on technical leadership to ensure new methodologies are adopted effectively across engineering teams.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Typically, 10+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products.
Strong hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification.
Deep understanding of timing signoff, constraints, STA debug, SDC methodology, multi-corner multi-mode closure, setup/hold optimization, and correlation across implementation and signoff tools.
Experience with power grid design, IR drop, EM analysis, low-power implementation, multi-voltage design, UPF-based flows, and power optimization techniques.
Proven ability to improve PPA through methodology innovation, tool tuning, automation, and cross-functional problem solving.
Strong scripting and automation skills using Tcl, Python, Perl, shell scripting, or equivalent technologies.
Experience working with leading EDA platforms from vendors such as Synopsys, Cadence, Siemens EDA, or equivalent tool ecosystems.
Demonstrated ability to influence technical direction, communicate complex topics clearly, and drive cross-team initiatives to closure.
Preferred Qualifications
Experience enabling advanced process nodes and supporting successful tapeouts on complex SoC, CPU, GPU, DSP, networking, automotive, or high-performance digital designs.
Familiarity with AI/ML-driven EDA optimization, design-space exploration, predictive analytics, automated debugging, and agentic workflow concepts.
Experience building production-quality flow infrastructure, regression frameworks, quality dashboards, and data pipelines for design implementation analytics.
Strong vendor engagement experience, including tool evaluation, benchmark definition, issue escalation, roadmap influence, and early technology adoption.
Ability to mentor engineers, define technical standards, and act as a trusted methodology expert across multiple design teams.
What Success Looks Like
Deployment of reliable, production-ready backend implementation flows that improve project execution efficiency and reduce design closure risk.
Measurable improvement in PPA, runtime, convergence predictability, and signoff correlation across advanced-node programs.
Successful evaluation and adoption of next-generation vendor capabilities, including ML/AI-based optimization and agentic automation technologies.
Strong cross-functional adoption of new methodologies through clear documentation, training, support, and continuous feedback loops.
Recognition as a senior technical leader who can translate emerging EDA technologies into practical, scalable, and high-impact design enablement solutions.
NXP Introduction:
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.
For more information, please visit our website https://www.nxp.com
Career Development Opportunities
The future starts here. Bright Minds. Bright Futures.
We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.
We Are NXP! Visit our careers website for more job information.
Commitment At NXP.
We recognize we can be a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.
Show more Show less