C
Principal Physical Design Engineer
Accepting applicationsChiparama · San Jose, CA
Full-Time Mid_senior ASICCadenceCalibreInnovusPERL
Posted
23 Apr
Category
Eda
Experience
Mid_senior
Country
United States
Seeking an Principal Physical Design Engineer specializing in DRC/LVS tapeout processes for advanced ASIC/SoC projects. This role focuses on top-level integration using Cadence Innovus, ensuring full-chip sign-off before manufacturing handoff.
Must Have:
Top Level Clock Build, Route, Extraction, Physical Verification, DRC, LVS Fix (Innovous, Calibre Tool Exposure Must)
Key Responsibilities
Execute DRC (Design Rule Checking) and LVS (Layout vs. Schematic) verification on top-level Innovus databases, integrating blocks, IOs, and power domains.
Drive tapeout readiness by resolving DRC/LVS violations, performing full-chip physical verification, and supporting digital-on-top flows.
Handle hierarchical sign-off, error debugging, and foundry rule compliance to enable high-volume semiconductor production.
Required Experience
12+ years in DRC/LVS tapeout with Cadence Innovus top-level flows for complex SoCs.
Proven hands-on expertise in full-chip verification, GDSII handling, and tapeout milestones at scale.
Familiarity with Synopsys tools (IC Validator), Calibre, or equivalent for physical verification decks.
Qualifications
B.S./M.S. in Electrical Engineering or related field. Strong scripting (TCL/PERL) and debugging skills essential for fast-paced semiconductor environments.
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Must Have:
Top Level Clock Build, Route, Extraction, Physical Verification, DRC, LVS Fix (Innovous, Calibre Tool Exposure Must)
Key Responsibilities
Execute DRC (Design Rule Checking) and LVS (Layout vs. Schematic) verification on top-level Innovus databases, integrating blocks, IOs, and power domains.
Drive tapeout readiness by resolving DRC/LVS violations, performing full-chip physical verification, and supporting digital-on-top flows.
Handle hierarchical sign-off, error debugging, and foundry rule compliance to enable high-volume semiconductor production.
Required Experience
12+ years in DRC/LVS tapeout with Cadence Innovus top-level flows for complex SoCs.
Proven hands-on expertise in full-chip verification, GDSII handling, and tapeout milestones at scale.
Familiarity with Synopsys tools (IC Validator), Calibre, or equivalent for physical verification decks.
Qualifications
B.S./M.S. in Electrical Engineering or related field. Strong scripting (TCL/PERL) and debugging skills essential for fast-paced semiconductor environments.
Show more Show less