Principal Engineer, Analog Layout (formerly Staff Engineer, Layout Design)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As an Analog Layout Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

Responsible for layout design of advanced SERDES and other analog and mixed signal macros in deep nanometer-level Fin-FET technologies. Plan and implement block-level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout DRC, LVS and other physical verification tools. Collaborate closely with circuit design teams to understand schematic requirements, optimize layout for performance, area, and power, and ensure first-pass silicon success. Perform advanced layout techniques for signal integrity, device matching, and low-noise design in high-speed and high-density environments. Participate in post-layout circuit performance analysis. Perform physical layout for custom structures in state-of-the-art nanometer-level CMOS technologies using Cadence tools. Assist in taking part in floor planning, custom layout and verifying against design rules and schematics. Apply strong understanding of ESD, latch-up, and reliability considerations to layout design practices. Develop realistic schedule for block-level layout including complete verifications. Lead and mentor a team of junior layout designers, providing technical guidance, reviews, and best practices for complex floorplans and block integration. Interface with packaging, DFT, and place & route teams to ensure smooth integration into the larger SoC environment. May telecommute. Reports to Santa Clara, CA. Wage $195,000.00 - $215,000.00 per year.

What We're Looking For

Bachelor’s degree or foreign degree equivalent in Electronic Engineering, Electrical Engineering, or related field and ten (10) years of hands-on experience with layout design in various blocks of RX, TX, PLL, ADC, DAC, or making Inductor layout.

Experience must include:

•    Five (5) years of experience leading the physical layout of high-speed SERDES circuits in FinFET technologies (7nm and below).
•    Four (4) years of experience with Scripting.
•    Ten (10) years of experience making integrated chips.
•    Seven (7) years of experience executing parasitic extraction (PEX) and working with circuit designers for post-layout simulation and optimization.

Employer will accept any job title in any occupation so long as requirements are met.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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