DS
Physical Design Engineers
Accepting applicationsDigicomm Semiconductor · Bengaluru, Karnataka, India
Full-Time Entry
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
22h ago
Category
Design
Experience
Entry
Country
India
Attention #Physical Design Engineers! Elevate your career to new horizons! Your quest concludes here – embrace the chance to embark on a transformative journey with Digicomm Semiconductor Private Limited as your next professional milestone.
Responsibilities
Physical Design Planning :Collaborate with chip architects and logic designers to understand the design goals, constraints, and specifications. Develop a physical design plan that outlines the steps and resources needed for successful implementation.
Floor planning: Create a floorplan that defines the placement of different functional blocks and components on the semiconductor die to optimize power, performance, and area (PPA).
Placement: Place and optimize logic cells, memory elements, and other IP blocks on the chip according to the floorplan. Balance trade-offs between area, timing, and power consumption.
Clock Tree Synthesis (CTS): Design and implement clock distribution networks to ensure synchronized clock signals throughout the chip, minimizing clock skew and jitter.
Qualifications
BTECH/MTECH
Experience
The Engineers with 2 to 8 years of Experience
Location
Bangalore/ Noida
Show more Show less
Responsibilities
Physical Design Planning :Collaborate with chip architects and logic designers to understand the design goals, constraints, and specifications. Develop a physical design plan that outlines the steps and resources needed for successful implementation.
Floor planning: Create a floorplan that defines the placement of different functional blocks and components on the semiconductor die to optimize power, performance, and area (PPA).
Placement: Place and optimize logic cells, memory elements, and other IP blocks on the chip according to the floorplan. Balance trade-offs between area, timing, and power consumption.
Clock Tree Synthesis (CTS): Design and implement clock distribution networks to ensure synchronized clock signals throughout the chip, minimizing clock skew and jitter.
Qualifications
BTECH/MTECH
Experience
The Engineers with 2 to 8 years of Experience
Location
Bangalore/ Noida
Show more Show less