VI
Physical Design Engineer
Accepting applicationsValue Innovation Labs · Sunnyvale, CA
Full-Time Entry ASICCadenceDFTInnovusPerl
Posted
21h ago
Category
Design
Experience
Entry
Country
United States
Physical Design Engineer – 3D-IC
Location: Sunnyvale, CA
Work Arrangement: Hybrid
Experience: 5–10 Years
Employment Type: Full-Time
Job Summary
We are seeking an experienced Physical Design Engineer – 3D-IC to join our semiconductor engineering team. The ideal candidate will have strong hands-on experience in ASIC/SoC Physical Design, including complete RTL-to-GDSII implementation, timing and physical signoff, and advanced-node tape-outs.
The candidate should have experience working with 5nm/3nm/2nm technologies, advanced physical design methodologies, and preferably 3D-IC, multi-die, or heterogeneous integration. Strong scripting skills, particularly Tcl, are required for methodology development and design automation.
Key ResponsibilitiesFull-Chip Physical Design
Own and execute the RTL-to-GDSII physical design flow from synthesis through final signoff.
Perform physical-aware synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
Drive design implementation to achieve timing, power, area, and quality-of-results (QoR) targets.
Perform timing closure and implement necessary ECOs throughout the design cycle.
3D-IC & Multi-Die Implementation
Support physical implementation of 3D-IC, 2.5D, heterogeneous integration, and multi-die architectures.
Perform TSV (Through-Silicon Via) planning and analyze die-to-die interconnect considerations.
Work with advanced packaging and 3D integration teams to address physical design challenges.
Analyze and resolve IR drop, electromigration (EM), thermal, and signal-integrity issues across multi-die designs.
Timing, Power & Signoff
Perform static timing analysis (STA) and drive timing closure for high-performance designs operating at 1GHz+.
Develop and execute MCMM/MMCM implementation and signoff strategies.
Analyze and resolve setup/hold violations, clock skew, crosstalk, and signal-integrity issues.
Implement low-power designs using UPF/CPF and support power-intent verification.
Perform or support IR-drop and EM analysis and physical signoff.
Methodology & Automation
Develop and maintain physical design methodologies and flows.
Create automation and productivity solutions using Tcl (mandatory), Python, and/or Perl.
Automate repetitive implementation, analysis, reporting, and signoff tasks.
Collaborate with IP, RTL, STA, DFT, packaging, foundry, and EDA teams to resolve implementation challenges.
Work with foundry and IP partners to ensure technology and design requirements are met.
Required Qualifications
5–10 years of hands-on experience in ASIC/SoC Physical Design.
Multiple successful full-cycle tape-outs from RTL through GDSII.
Experience with advanced semiconductor process nodes, preferably 5nm, 3nm, or 2nm.
Strong understanding of the complete RTL-to-GDSII implementation flow.
Strong experience with floorplanning, placement, CTS, routing, optimization, and timing closure.
Hands-on experience with MCMM/MMCM, STA, signal integrity, IR drop, and EM analysis.
Experience implementing high-frequency designs (1GHz+).
Experience with low-power design methodologies using UPF/CPF.
Strong hands-on experience with one or more industry-standard EDA flows:
Cadence: Innovus, Tempus, Voltus
Synopsys: ICC2, PrimeTime
Strong Tcl scripting skills – mandatory.
Proficiency in Python and/or Perl is highly desirable.
Strong problem-solving and debugging skills with the ability to work across multiple design disciplines.
Show more Show less
Location: Sunnyvale, CA
Work Arrangement: Hybrid
Experience: 5–10 Years
Employment Type: Full-Time
Job Summary
We are seeking an experienced Physical Design Engineer – 3D-IC to join our semiconductor engineering team. The ideal candidate will have strong hands-on experience in ASIC/SoC Physical Design, including complete RTL-to-GDSII implementation, timing and physical signoff, and advanced-node tape-outs.
The candidate should have experience working with 5nm/3nm/2nm technologies, advanced physical design methodologies, and preferably 3D-IC, multi-die, or heterogeneous integration. Strong scripting skills, particularly Tcl, are required for methodology development and design automation.
Key ResponsibilitiesFull-Chip Physical Design
Own and execute the RTL-to-GDSII physical design flow from synthesis through final signoff.
Perform physical-aware synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
Drive design implementation to achieve timing, power, area, and quality-of-results (QoR) targets.
Perform timing closure and implement necessary ECOs throughout the design cycle.
3D-IC & Multi-Die Implementation
Support physical implementation of 3D-IC, 2.5D, heterogeneous integration, and multi-die architectures.
Perform TSV (Through-Silicon Via) planning and analyze die-to-die interconnect considerations.
Work with advanced packaging and 3D integration teams to address physical design challenges.
Analyze and resolve IR drop, electromigration (EM), thermal, and signal-integrity issues across multi-die designs.
Timing, Power & Signoff
Perform static timing analysis (STA) and drive timing closure for high-performance designs operating at 1GHz+.
Develop and execute MCMM/MMCM implementation and signoff strategies.
Analyze and resolve setup/hold violations, clock skew, crosstalk, and signal-integrity issues.
Implement low-power designs using UPF/CPF and support power-intent verification.
Perform or support IR-drop and EM analysis and physical signoff.
Methodology & Automation
Develop and maintain physical design methodologies and flows.
Create automation and productivity solutions using Tcl (mandatory), Python, and/or Perl.
Automate repetitive implementation, analysis, reporting, and signoff tasks.
Collaborate with IP, RTL, STA, DFT, packaging, foundry, and EDA teams to resolve implementation challenges.
Work with foundry and IP partners to ensure technology and design requirements are met.
Required Qualifications
5–10 years of hands-on experience in ASIC/SoC Physical Design.
Multiple successful full-cycle tape-outs from RTL through GDSII.
Experience with advanced semiconductor process nodes, preferably 5nm, 3nm, or 2nm.
Strong understanding of the complete RTL-to-GDSII implementation flow.
Strong experience with floorplanning, placement, CTS, routing, optimization, and timing closure.
Hands-on experience with MCMM/MMCM, STA, signal integrity, IR drop, and EM analysis.
Experience implementing high-frequency designs (1GHz+).
Experience with low-power design methodologies using UPF/CPF.
Strong hands-on experience with one or more industry-standard EDA flows:
Cadence: Innovus, Tempus, Voltus
Synopsys: ICC2, PrimeTime
Strong Tcl scripting skills – mandatory.
Proficiency in Python and/or Perl is highly desirable.
Strong problem-solving and debugging skills with the ability to work across multiple design disciplines.
Show more Show less