TI
Physical Design Engineer
Accepting applicationsTriveni IT · San Jose, CA
Contract Mid_senior AICadenceGenusInnovusRTL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Role: Physical Design Engineer
Duration: long term contract
Location: San Jose CA.
About the Company
We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes.
Responsibilities
Proven experience with large-scale SoC or AI-class designs
At least 5 years of PD experience
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation team
Required Skills
Proven experience with large-scale SoC or AI-class designs
At least 5 years of PD experience
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation team
Show more Show less
Duration: long term contract
Location: San Jose CA.
About the Company
We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes.
Responsibilities
Proven experience with large-scale SoC or AI-class designs
At least 5 years of PD experience
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation team
Required Skills
Proven experience with large-scale SoC or AI-class designs
At least 5 years of PD experience
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation team
Show more Show less