MT
Physical Design Engineer
Accepting applicationsMirafra Technologies · Santa Clara, CA
Full-Time Mid_senior AIDFTPerlPythonRTL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
About the Role
As a Physical Design Engineer at Intel, you will play a pivotal role in shaping next-generation custom IP and complex System-on-Chip (SoC) designs across client, data center, and AI computing platforms. In this role, you will own the full RTL-to-GDSII physical implementation flow, driving state-of-the-art semiconductor process nodes to push the boundaries of Power, Performance, and Area (PPA). You will collaborate closely with architecture, logic design, DFT, and process technology teams to deliver manufacturing-ready silicon.
Key Responsibilities
RTL-to-GDSII Implementation: Perform physical design tasks from synthesis to layout signoff on complex IP blocks and multi-million gate SoC designs.
Floor planning & PnR: Execute block-level and full-chip floor planning, power grid design, placement, Clock Tree Synthesis (CTS), and routing using industry-standard EDA tools.
Timing Closure: Conduct Static Timing Analysis (STA), multi-corner/multi-mode (MCMM) timing validation, constraint development, and timing signoff closure.
Power & Reliability Signoff: Perform dynamic and static power integrity (IR-drop) analysis, electromigration (EM) checks, and formal equivalence verification (FEV).
Physical Verification: Debug and resolve DRC, LVS, ERC, and antenna rules to ensure layout integrity for manufacturing tape-out.
Low-Power Design: Implement advanced low-power methodologies using UPF/CPF standards, multi-voltage domains, power gating, and retention logic.
Flow & Automation Development: Develop custom Tcl, Python, and Perl scripts to automate physical design flows, optimize EDA tool runs, and enhance design productivity.
Cross-Functional Collaboration: Partner with architecture, logic verification, synthesis, and layout teams to troubleshoot complex design challenges and refine timing/power trade-offs.
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As a Physical Design Engineer at Intel, you will play a pivotal role in shaping next-generation custom IP and complex System-on-Chip (SoC) designs across client, data center, and AI computing platforms. In this role, you will own the full RTL-to-GDSII physical implementation flow, driving state-of-the-art semiconductor process nodes to push the boundaries of Power, Performance, and Area (PPA). You will collaborate closely with architecture, logic design, DFT, and process technology teams to deliver manufacturing-ready silicon.
Key Responsibilities
RTL-to-GDSII Implementation: Perform physical design tasks from synthesis to layout signoff on complex IP blocks and multi-million gate SoC designs.
Floor planning & PnR: Execute block-level and full-chip floor planning, power grid design, placement, Clock Tree Synthesis (CTS), and routing using industry-standard EDA tools.
Timing Closure: Conduct Static Timing Analysis (STA), multi-corner/multi-mode (MCMM) timing validation, constraint development, and timing signoff closure.
Power & Reliability Signoff: Perform dynamic and static power integrity (IR-drop) analysis, electromigration (EM) checks, and formal equivalence verification (FEV).
Physical Verification: Debug and resolve DRC, LVS, ERC, and antenna rules to ensure layout integrity for manufacturing tape-out.
Low-Power Design: Implement advanced low-power methodologies using UPF/CPF standards, multi-voltage domains, power gating, and retention logic.
Flow & Automation Development: Develop custom Tcl, Python, and Perl scripts to automate physical design flows, optimize EDA tool runs, and enhance design productivity.
Cross-Functional Collaboration: Partner with architecture, logic verification, synthesis, and layout teams to troubleshoot complex design challenges and refine timing/power trade-offs.
Show more Show less