JV
Physical Design Engineer
Accepting applicationsJobs via Dice · Sunnyvale, CA
Full-Time Mid CadenceCalibreFinFETInnovusPerl
Posted
1d ago
Category
Eda
Experience
Mid
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, Reveille Technologies, is seeking the following. Apply via Dice today!
Only Local independent candidates are allowed to apply for this Role.
Location: Sunnyvale, CA | Austin, TX Experience: 10+ years
Brief: Lead RTL-to-GDSII implementation for high-performance SoCs on 3nm/5nm nodes. Focus on PnR, timing closure, and power integrity.
Core Tech Stack:
Tools: Cadence Innovus or Synopsys ICC2/Fusion Compiler.
Sign-off: PrimeTime (STA), RedHawk/Voltus (Power), Calibre (PV).
Scripting: Python, Tcl, or Perl.
Requirements:
Proven track record with FinFET (5nm or below).
Expert in STA, CTS, and EM/IR analysis.
BS/MS in Electrical Engineering or VLSI. Thanks and Regards,
Praveenkumar
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Only Local independent candidates are allowed to apply for this Role.
Location: Sunnyvale, CA | Austin, TX Experience: 10+ years
Brief: Lead RTL-to-GDSII implementation for high-performance SoCs on 3nm/5nm nodes. Focus on PnR, timing closure, and power integrity.
Core Tech Stack:
Tools: Cadence Innovus or Synopsys ICC2/Fusion Compiler.
Sign-off: PrimeTime (STA), RedHawk/Voltus (Power), Calibre (PV).
Scripting: Python, Tcl, or Perl.
Requirements:
Proven track record with FinFET (5nm or below).
Expert in STA, CTS, and EM/IR analysis.
BS/MS in Electrical Engineering or VLSI. Thanks and Regards,
Praveenkumar
Show more Show less