AT
Physical Design Engineer
Accepting applicationsAcceler8 Talent · Mountain View, CA
Full-Time Mid_senior AIASICInnovusaiate
Posted
21 Apr
Category
Design
Experience
Mid_senior
Country
United States
Acceler8 Talent is partnering with an early-stage startup to hire a Physical Design Engineer.
The team is focused on advancing silicon design through innovations in wafer-scale systems and advanced 3D heterogeneous integration, developing next-generation AI hardware platforms that push beyond conventional design approaches.
This position involves driving physical implementation for high-performance AI silicon, with responsibilities spanning both block-level and full-chip design. The role goes beyond traditional physical design, contributing to a new class of compute architecture and requiring close collaboration across multiple engineering domains.
Key Responsibilities
Lead physical design efforts from block-level implementation through full-chip integration
Execute place-and-route for complex, high-performance ASIC designs
Drive timing closure, power optimization, and final physical verification
Identify and resolve physical design issues, including DRC, LVS, IR drop, and electromigration concerns
Partner with front-end teams on floorplanning, constraints, and design trade-offs
Develop and improve physical design methodologies, flows, and automation
Support integration strategies involving advanced packaging technologies, including multi-die systems
Qualifications
Strong background in ASIC physical design, including place-and-route and timing closure
Hands-on experience with industry-standard tools (e.g., ICC2, Innovus, or similar)
Solid understanding of physical verification and signoff processes (e.g., DRC, LVS, IR drop, EM)
Experience working on complex system-on-chip designs
Familiarity with advanced semiconductor nodes (e.g., 7nm or below)
Experience with advanced packaging approaches such as 2.5D or 3D integration
Background in high-performance compute or similar demanding design environments
Scripting or automation experience to improve design efficiency
Leveling & Expectations
*Opportunities available at senior through principal levels, depending on scope and experience
Expected to take ownership of major subsystems or full-chip implementation
Ability to collaborate across teams and drive execution through tapeout
Comfortable operating in a fast-paced environment with evolving requirements
Show more Show less
The team is focused on advancing silicon design through innovations in wafer-scale systems and advanced 3D heterogeneous integration, developing next-generation AI hardware platforms that push beyond conventional design approaches.
This position involves driving physical implementation for high-performance AI silicon, with responsibilities spanning both block-level and full-chip design. The role goes beyond traditional physical design, contributing to a new class of compute architecture and requiring close collaboration across multiple engineering domains.
Key Responsibilities
Lead physical design efforts from block-level implementation through full-chip integration
Execute place-and-route for complex, high-performance ASIC designs
Drive timing closure, power optimization, and final physical verification
Identify and resolve physical design issues, including DRC, LVS, IR drop, and electromigration concerns
Partner with front-end teams on floorplanning, constraints, and design trade-offs
Develop and improve physical design methodologies, flows, and automation
Support integration strategies involving advanced packaging technologies, including multi-die systems
Qualifications
Strong background in ASIC physical design, including place-and-route and timing closure
Hands-on experience with industry-standard tools (e.g., ICC2, Innovus, or similar)
Solid understanding of physical verification and signoff processes (e.g., DRC, LVS, IR drop, EM)
Experience working on complex system-on-chip designs
Familiarity with advanced semiconductor nodes (e.g., 7nm or below)
Experience with advanced packaging approaches such as 2.5D or 3D integration
Background in high-performance compute or similar demanding design environments
Scripting or automation experience to improve design efficiency
Leveling & Expectations
*Opportunities available at senior through principal levels, depending on scope and experience
Expected to take ownership of major subsystems or full-chip implementation
Ability to collaborate across teams and drive execution through tapeout
Comfortable operating in a fast-paced environment with evolving requirements
Show more Show less