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Physical Design Engineer(2-8 YOE)
Accepting applicationsSiliconBoard · Bengaluru, Karnataka, India
Full-Time Entry AIASICRTLSoCVLSI
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Entry
Country
India
Job: Physical Design Engineer(2-8 YOE)
Location: Bengaluru | Noida
Employment Type: Full-time
Experience: 2–8 years
Function: Semiconductor Engineering — Physical Design
About SiliconBoard
SiliconBoard connects semiconductor engineering talent with companies across the semiconductor ecosystem. This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are evaluated and shared with hiring companies within our partner network for relevant open positions.
About the Role
We are looking for experienced Physical Design Engineers with hands-on experience in ASIC physical implementation.
You will work on physical design from planning and floorplanning through placement, clock implementation, optimization, and design closure.
The role involves working with architecture, RTL, timing, and implementation teams to meet power, performance, and area (PPA) targets.
Key Responsibilities
Physical Design Planning
Understand design specifications, constraints, architecture, and implementation requirements.
Work with chip architects, logic designers, and implementation teams to define the physical design strategy.
Plan the implementation flow based on timing, area, power, and design constraints.
Floorplanning
Develop block-level and chip-level floorplans.
Plan macro and standard-cell placement.
Define physical regions and placement constraints.
Optimize floorplans for timing, area, routability, and power.
Identify and resolve early congestion and implementation issues.
Placement & Optimization
Perform placement and optimization of standard cells, memory blocks, and IP.
Analyze timing, congestion, utilization, and power during implementation.
Optimize the design to meet PPA targets.
Debug implementation issues and drive design convergence.
Clock Tree Synthesis
Implement and optimize clock distribution networks.
Control clock skew, latency, transition, and insertion delay.
Analyze clock-related timing issues and work toward timing closure.
Debug CTS and post-CTS implementation issues.
Design Closure
Analyze setup and hold timing issues across implementation stages.
Work with timing, RTL, and implementation teams to resolve violations.
Support routing, physical verification, and implementation sign-off activities.
Track design quality through the implementation flow.
Required Qualifications
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
2–8 years of hands-on industry experience in ASIC Physical Design.
Experience with physical design planning and floorplanning.
Hands-on experience with placement and optimization.
Experience with Clock Tree Synthesis (CTS).
Good understanding of timing, area, power, congestion, and routability trade-offs.
Understanding of digital design and ASIC implementation fundamentals.
Ability to debug physical implementation and timing-related issues.
Preferred Qualifications
Relevant experience in one or more of the following areas:
Floorplanning
Macro placement
Placement optimization
Clock Tree Synthesis
Static Timing Analysis
Setup and hold timing closure
Congestion analysis
Power planning
Routing
Physical verification
PPA optimization
Block-level implementation
SoC physical implementation
Design sign-off
Experience working with industry-standard ASIC physical design, STA, and sign-off tools is preferred.
Hiring Process
Submit your resume through the application link.
Profiles are manually reviewed and shortlisted by the SiliconBoard team.
Shortlisted candidates may receive a technical screening or AI-based technical interview.
Qualified profiles are shared with the hiring company for the next stage of the process.
Additional Information
This opportunity is with a SiliconBoard client company and not with SiliconBoard directly.
Compensation is determined by the hiring company based on role, experience, technical depth, and interview performance.
Submission of an application does not guarantee an interview, referral, or employment. Profiles are evaluated based on physical design experience, implementation depth, project experience, timing and PPA knowledge, and the requirements of the hiring company.
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Location: Bengaluru | Noida
Employment Type: Full-time
Experience: 2–8 years
Function: Semiconductor Engineering — Physical Design
About SiliconBoard
SiliconBoard connects semiconductor engineering talent with companies across the semiconductor ecosystem. This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are evaluated and shared with hiring companies within our partner network for relevant open positions.
About the Role
We are looking for experienced Physical Design Engineers with hands-on experience in ASIC physical implementation.
You will work on physical design from planning and floorplanning through placement, clock implementation, optimization, and design closure.
The role involves working with architecture, RTL, timing, and implementation teams to meet power, performance, and area (PPA) targets.
Key Responsibilities
Physical Design Planning
Understand design specifications, constraints, architecture, and implementation requirements.
Work with chip architects, logic designers, and implementation teams to define the physical design strategy.
Plan the implementation flow based on timing, area, power, and design constraints.
Floorplanning
Develop block-level and chip-level floorplans.
Plan macro and standard-cell placement.
Define physical regions and placement constraints.
Optimize floorplans for timing, area, routability, and power.
Identify and resolve early congestion and implementation issues.
Placement & Optimization
Perform placement and optimization of standard cells, memory blocks, and IP.
Analyze timing, congestion, utilization, and power during implementation.
Optimize the design to meet PPA targets.
Debug implementation issues and drive design convergence.
Clock Tree Synthesis
Implement and optimize clock distribution networks.
Control clock skew, latency, transition, and insertion delay.
Analyze clock-related timing issues and work toward timing closure.
Debug CTS and post-CTS implementation issues.
Design Closure
Analyze setup and hold timing issues across implementation stages.
Work with timing, RTL, and implementation teams to resolve violations.
Support routing, physical verification, and implementation sign-off activities.
Track design quality through the implementation flow.
Required Qualifications
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
2–8 years of hands-on industry experience in ASIC Physical Design.
Experience with physical design planning and floorplanning.
Hands-on experience with placement and optimization.
Experience with Clock Tree Synthesis (CTS).
Good understanding of timing, area, power, congestion, and routability trade-offs.
Understanding of digital design and ASIC implementation fundamentals.
Ability to debug physical implementation and timing-related issues.
Preferred Qualifications
Relevant experience in one or more of the following areas:
Floorplanning
Macro placement
Placement optimization
Clock Tree Synthesis
Static Timing Analysis
Setup and hold timing closure
Congestion analysis
Power planning
Routing
Physical verification
PPA optimization
Block-level implementation
SoC physical implementation
Design sign-off
Experience working with industry-standard ASIC physical design, STA, and sign-off tools is preferred.
Hiring Process
Submit your resume through the application link.
Profiles are manually reviewed and shortlisted by the SiliconBoard team.
Shortlisted candidates may receive a technical screening or AI-based technical interview.
Qualified profiles are shared with the hiring company for the next stage of the process.
Additional Information
This opportunity is with a SiliconBoard client company and not with SiliconBoard directly.
Compensation is determined by the hiring company based on role, experience, technical depth, and interview performance.
Submission of an application does not guarantee an interview, referral, or employment. Profiles are evaluated based on physical design experience, implementation depth, project experience, timing and PPA knowledge, and the requirements of the hiring company.
Show more Show less