LD
Physical Design - 10+ Years - Bangalore Location
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru South, Karnataka, India
Full-Time Entry AIASICCadenceCalibreDDR
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Design
Experience
Entry
Country
India
Company Description LeadIC Design Pvt Ltd is a full-stack VLSI engineering company focused on accelerating semiconductor innovation for global product-driven teams. Founded in 2018, the company supports the complete chip development lifecycle with strong technical depth, accountable execution, and flexible engagement models. Engineering teams based in India and Canada deliver high-quality services across digital design, verification, physical design, layout, STA, DFT, and FPGA-based prototyping. LeadIC’s culture emphasizes ownership, quality-driven methodologies, and scalable offshore development centers that operate as an extension of client teams. Long-term partnerships with leading semiconductor companies reflect the reliability and value LeadIC brings to complex silicon programs.
Role Description
We are looking for an experienced Lead Physical Design Engineer with 10+ years of hands-on experience in digital Physical Design to lead the implementation of complex ASIC/SoC designs from netlist to GDSII.
The candidate will be responsible for driving end-to-end physical implementation, timing closure, PPA optimization, physical signoff and tapeout, while providing technical leadership and mentoring to the Physical Design team.
Key Responsibilities
Lead end-to-end Physical Design implementation from netlist to GDSII/tapeout.
Own and drive floorplanning, power planning, placement, CTS, routing and physical optimization.
Drive setup/hold timing closure across multiple modes and PVT corners.
Perform MCMM/MMMC analysis and optimization for timing, area, power and congestion.
Drive clock-tree implementation and optimization, including skew, latency, transition and clock-related constraints.
Analyze and resolve congestion, DRV, timing, routing and signal-integrity issues.
Handle ECO implementation and timing convergence through signoff.
Work closely with STA, RTL, Synthesis, DFT, Physical Verification, CAD and Signoff teams.
Drive IR drop, EM, power integrity and signal-integrity closure in collaboration with signoff teams.
Support and resolve DRC, LVS, Antenna and other physical verification issues.
Own block/subsystem integration and contribute to full-chip implementation and signoff.
Define and improve Physical Design methodologies, flows and QoR metrics.
Develop automation and productivity solutions using Tcl/Python/Perl/Shell scripting.
Debug complex implementation issues and provide technical solutions to achieve PPA and schedule targets.
Mentor junior and senior engineers and provide technical guidance to the PD team.
Participate in project planning, execution tracking, risk identification and tapeout readiness.
Drive continuous improvement in PD flow, methodology, automation and signoff quality.
Mandatory Skills
10+ years of hands-on Physical Design / ASIC implementation experience.
Strong experience in RTL-to-GDSII / Netlist-to-GDSII flow.
Excellent hands-on experience with Cadence Innovus and/or Synopsys ICC2/Fusion Compiler.
Strong expertise in:
Floorplanning
Power planning
Placement
CTS
Routing
Physical optimization
Timing closure
ECO
Strong knowledge of STA, SDC and timing constraints.
Hands-on experience with MCMM/MMMC timing closure.
Good understanding of setup/hold, OCV/AOCV/POCV, CPPR and SI effects.
Strong knowledge of Physical Verification – DRC/LVS/Antenna.
Good understanding of IR/EM and power integrity.
Experience with advanced technology nodes, preferably 7nm/5nm/3nm or below.
Strong Tcl scripting skills; Python/Perl/Shell scripting is an advantage.
Experience in tapeout/signoff of complex SoC/ASIC designs.
Proven experience in technical leadership and mentoring.
Current Bangalore roles at companies such as Rambus, NXP, AMD and L&T Semiconductor Technologies similarly emphasize end-to-end implementation, Innovus/industry-standard tools, STA/timing closure, physical verification, IR/EM, advanced nodes, automation and technical leadership.
Good to Have
Experience with FinFET / advanced-node designs.
Experience in high-performance CPU/GPU/AI/Networking/SerDes/DDR/PCIe designs.
Experience with full-chip/top-level integration.
Exposure to low-power design methodologies – UPF/CPF.
Experience with Cadence Tempus / Voltus / Pegasus.
Experience with Synopsys PrimeTime / StarRC.
Exposure to Calibre / RedHawk / Ansys signoff tools.
Experience with hierarchical P&R and partition-level implementation.
Strong understanding of PPA optimization and design convergence.
Experience in developing PD methodologies and flow automation.
Show more Show less
Role Description
We are looking for an experienced Lead Physical Design Engineer with 10+ years of hands-on experience in digital Physical Design to lead the implementation of complex ASIC/SoC designs from netlist to GDSII.
The candidate will be responsible for driving end-to-end physical implementation, timing closure, PPA optimization, physical signoff and tapeout, while providing technical leadership and mentoring to the Physical Design team.
Key Responsibilities
Lead end-to-end Physical Design implementation from netlist to GDSII/tapeout.
Own and drive floorplanning, power planning, placement, CTS, routing and physical optimization.
Drive setup/hold timing closure across multiple modes and PVT corners.
Perform MCMM/MMMC analysis and optimization for timing, area, power and congestion.
Drive clock-tree implementation and optimization, including skew, latency, transition and clock-related constraints.
Analyze and resolve congestion, DRV, timing, routing and signal-integrity issues.
Handle ECO implementation and timing convergence through signoff.
Work closely with STA, RTL, Synthesis, DFT, Physical Verification, CAD and Signoff teams.
Drive IR drop, EM, power integrity and signal-integrity closure in collaboration with signoff teams.
Support and resolve DRC, LVS, Antenna and other physical verification issues.
Own block/subsystem integration and contribute to full-chip implementation and signoff.
Define and improve Physical Design methodologies, flows and QoR metrics.
Develop automation and productivity solutions using Tcl/Python/Perl/Shell scripting.
Debug complex implementation issues and provide technical solutions to achieve PPA and schedule targets.
Mentor junior and senior engineers and provide technical guidance to the PD team.
Participate in project planning, execution tracking, risk identification and tapeout readiness.
Drive continuous improvement in PD flow, methodology, automation and signoff quality.
Mandatory Skills
10+ years of hands-on Physical Design / ASIC implementation experience.
Strong experience in RTL-to-GDSII / Netlist-to-GDSII flow.
Excellent hands-on experience with Cadence Innovus and/or Synopsys ICC2/Fusion Compiler.
Strong expertise in:
Floorplanning
Power planning
Placement
CTS
Routing
Physical optimization
Timing closure
ECO
Strong knowledge of STA, SDC and timing constraints.
Hands-on experience with MCMM/MMMC timing closure.
Good understanding of setup/hold, OCV/AOCV/POCV, CPPR and SI effects.
Strong knowledge of Physical Verification – DRC/LVS/Antenna.
Good understanding of IR/EM and power integrity.
Experience with advanced technology nodes, preferably 7nm/5nm/3nm or below.
Strong Tcl scripting skills; Python/Perl/Shell scripting is an advantage.
Experience in tapeout/signoff of complex SoC/ASIC designs.
Proven experience in technical leadership and mentoring.
Current Bangalore roles at companies such as Rambus, NXP, AMD and L&T Semiconductor Technologies similarly emphasize end-to-end implementation, Innovus/industry-standard tools, STA/timing closure, physical verification, IR/EM, advanced nodes, automation and technical leadership.
Good to Have
Experience with FinFET / advanced-node designs.
Experience in high-performance CPU/GPU/AI/Networking/SerDes/DDR/PCIe designs.
Experience with full-chip/top-level integration.
Exposure to low-power design methodologies – UPF/CPF.
Experience with Cadence Tempus / Voltus / Pegasus.
Experience with Synopsys PrimeTime / StarRC.
Exposure to Calibre / RedHawk / Ansys signoff tools.
Experience with hierarchical P&R and partition-level implementation.
Strong understanding of PPA optimization and design convergence.
Experience in developing PD methodologies and flow automation.
Show more Show less