MS
MTS/SMTS Pre-Silicon Validation Engineer
Accepting applicationsMettlesemi Systems and Technologies Private Limited · Bengaluru, Karnataka, India
Full-Time Mid EthernetPCIePythonRTLSoC
Estimated market salary
₹11-17 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Mid
Country
India
Candidate Qualifications
Minimum qualifications:
Bachelor’s degree in Electrical Engineering or Computer Science
Relevant experience: 5-10 years
Preferred Qualifications
Development of emulation prototypes of a 5G SoC for functional and performance validation
Good knowledge of digital design and RTL implementation in verilog/system-verilog is a strong requirement
Experience in emulator tool chains and flows – synthesis, timing closure, P&R – is a must have
Good understanding of on-board components like clocking and interfaces (PCIe/Ethernet)
Must be able to comprehend complex designs and methods to effectively prototype them
Good understanding of AMBA protocols (AXI4, APB) required
Experience with multiple clock domains and asynchronous interfaces
Knowledge of system architecture, CPU & IP Integration, and clock management designs desirable
Basic understanding of system-verilog based verification preferred
Experience in wireless communication design (4G/5G) is preferred
Ability to communicate effectively across all internal groups
Familiarity with scripting languages like Python is a plus
Location: Bangalore, India
Show more Show less
Minimum qualifications:
Bachelor’s degree in Electrical Engineering or Computer Science
Relevant experience: 5-10 years
Preferred Qualifications
Development of emulation prototypes of a 5G SoC for functional and performance validation
Good knowledge of digital design and RTL implementation in verilog/system-verilog is a strong requirement
Experience in emulator tool chains and flows – synthesis, timing closure, P&R – is a must have
Good understanding of on-board components like clocking and interfaces (PCIe/Ethernet)
Must be able to comprehend complex designs and methods to effectively prototype them
Good understanding of AMBA protocols (AXI4, APB) required
Experience with multiple clock domains and asynchronous interfaces
Knowledge of system architecture, CPU & IP Integration, and clock management designs desirable
Basic understanding of system-verilog based verification preferred
Experience in wireless communication design (4G/5G) is preferred
Ability to communicate effectively across all internal groups
Familiarity with scripting languages like Python is a plus
Location: Bangalore, India
Show more Show less