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Lead STA Engineer – Static Timing Analysis
Accepting applicationsAsian Hires · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICPerlPythonSOCSynopsys
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Experience: 9–15 Years
Position: 1
CTC: ₹20–24 LPA
About the Role
We are looking for an experienced Lead STA Engineer with strong hands-on expertise in Static Timing Analysis (STA) and ASIC design flows. The ideal candidate should have solid experience with PrimeTime or equivalent STA tools, DMSA, ECO generation, timing closure, and close collaboration with PNR, synthesis, and design teams.
This is a highly technical STA/Timing role. Candidates with only general ASIC/VLSI experience and limited hands-on STA exposure will not be considered.
Key Responsibilities
Perform Static Timing Analysis (STA) and provide timing feedback to PNR teams.
Work extensively with Synopsys PrimeTime or equivalent STA tools.
Generate and analyze ECOs using DMSA.
Analyze timing reports, identify timing violations and recommend corrective actions.
Work closely with PNR, synthesis and design teams to achieve timing closure.
Support ASIC design flows, particularly at advanced/sub-7nm technology nodes.
Support synthesis, physical design and timing closure activities.
Perform low-power digital design and timing analysis as required.
Develop and maintain automation scripts using TCL, Perl and/or Python.
Work extensively in a Linux environment.
Communicate and present complex technical information effectively.
Mandatory Skills
7+ years industry experience; 9+ years preferred
Strong hands-on STA / Timing Analysis
Synopsys PrimeTime or equivalent
DMSA and ECO generation
Timing feedback and closure with PNR teams
ASIC/SOC experience at sub-7nm technology nodes
Strong understanding of synthesis and physical design flows
Experience with Synopsys Fusion Compiler, PrimeTime and RedHawk
Strong TCL, Perl and/or Python scripting
Strong Linux experience
Good communication and technical presentation skills
Preferred Profile
Candidates with strong experience in timing closure, advanced-node ASIC/SOC design, low-power digital design and Synopsys implementation/signoff flows will be preferred.
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Position: 1
CTC: ₹20–24 LPA
About the Role
We are looking for an experienced Lead STA Engineer with strong hands-on expertise in Static Timing Analysis (STA) and ASIC design flows. The ideal candidate should have solid experience with PrimeTime or equivalent STA tools, DMSA, ECO generation, timing closure, and close collaboration with PNR, synthesis, and design teams.
This is a highly technical STA/Timing role. Candidates with only general ASIC/VLSI experience and limited hands-on STA exposure will not be considered.
Key Responsibilities
Perform Static Timing Analysis (STA) and provide timing feedback to PNR teams.
Work extensively with Synopsys PrimeTime or equivalent STA tools.
Generate and analyze ECOs using DMSA.
Analyze timing reports, identify timing violations and recommend corrective actions.
Work closely with PNR, synthesis and design teams to achieve timing closure.
Support ASIC design flows, particularly at advanced/sub-7nm technology nodes.
Support synthesis, physical design and timing closure activities.
Perform low-power digital design and timing analysis as required.
Develop and maintain automation scripts using TCL, Perl and/or Python.
Work extensively in a Linux environment.
Communicate and present complex technical information effectively.
Mandatory Skills
7+ years industry experience; 9+ years preferred
Strong hands-on STA / Timing Analysis
Synopsys PrimeTime or equivalent
DMSA and ECO generation
Timing feedback and closure with PNR teams
ASIC/SOC experience at sub-7nm technology nodes
Strong understanding of synthesis and physical design flows
Experience with Synopsys Fusion Compiler, PrimeTime and RedHawk
Strong TCL, Perl and/or Python scripting
Strong Linux experience
Good communication and technical presentation skills
Preferred Profile
Candidates with strong experience in timing closure, advanced-node ASIC/SOC design, low-power digital design and Synopsys implementation/signoff flows will be preferred.
Show more Show less