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Lead ASIC Chip Design Engineer
Accepting applicationsCypress HCM · Brooklyn Park, MN
Full-Time Mid_senior ASICAnalogC++MentorPerl
Posted
22h ago
Category
Design
Experience
Mid_senior
Country
United States
We are seeking an experienced ASIC Chip Design Lead to contribute to the development of complex, custom-designed integrated circuits. This is a hands-on technical leadership role spanning the full chip development lifecycle, from architecture and RTL design through synthesis, timing closure, physical implementation, and verification.
The ideal candidate is a highly capable digital IC designer who remains hands-on with complex block development and has strong knowledge of the complete ASIC/SoC design flow. Experience with specialized semiconductor technologies, mixed-signal environments, processor-based designs, or standard-cell development is a plus.
Responsibilities
Lead ASIC/SoC architecture and development based on system-level requirements.
Work with system and design teams to define functionality, interfaces, specifications, and performance goals.
Design and implement complex digital blocks using Verilog/SystemVerilog.
Develop and optimize RTL for power, performance, and area.
Perform synthesis and analyze results using industry-standard EDA tools.
Develop timing constraints and support timing closure across the design.
Collaborate closely with physical design engineers on floorplanning, placement, routing, and design closure.
Support processor integration, constraint development, and performance optimization.
Partner with verification engineers to ensure functional correctness and robust design implementation.
Contribute to design methodology improvements, development processes, and engineering best practices.
Evaluate technical requirements and provide input on project scope, effort, and resource needs.
Work effectively within a collaborative, distributed engineering environment.
Mentor and provide technical guidance to less-experienced engineers.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent experience.
10+ years of industry experience in ASIC and/or SoC design.
Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
Demonstrated experience across multiple stages of the ASIC/SoC development flow.
Experience with synthesis and industry-standard EDA tools.
Strong understanding of digital design, timing, constraints, and implementation concepts.
Experience working with processor-based SoC designs or RISC architectures.
Proficiency in Linux/UNIX environments and scripting.
Experience with programming or scripting languages such as Python, Perl, Tcl, C/C++, or similar.
Familiarity with modern source-control systems and collaborative engineering workflows.
Strong analytical, problem-solving, and communication skills.
Ability to take ownership of technically challenging projects and work effectively in a team environment.
Demonstrated ability to mentor engineers and provide technical leadership.
Preferred Qualifications
Experience with radiation-tolerant or reliability-focused semiconductor design.
Analog/mixed-signal design experience or familiarity with mixed-signal development environments.
Experience with standard-cell libraries or related semiconductor IP.
Experience taking complex ASIC/SoC designs successfully through fabrication.
Familiarity with additional EDA tools and advanced design methodologies.
Salary of $150,000 to $205,000 annually (salary depends on experience level, education and qualifications)
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The ideal candidate is a highly capable digital IC designer who remains hands-on with complex block development and has strong knowledge of the complete ASIC/SoC design flow. Experience with specialized semiconductor technologies, mixed-signal environments, processor-based designs, or standard-cell development is a plus.
Responsibilities
Lead ASIC/SoC architecture and development based on system-level requirements.
Work with system and design teams to define functionality, interfaces, specifications, and performance goals.
Design and implement complex digital blocks using Verilog/SystemVerilog.
Develop and optimize RTL for power, performance, and area.
Perform synthesis and analyze results using industry-standard EDA tools.
Develop timing constraints and support timing closure across the design.
Collaborate closely with physical design engineers on floorplanning, placement, routing, and design closure.
Support processor integration, constraint development, and performance optimization.
Partner with verification engineers to ensure functional correctness and robust design implementation.
Contribute to design methodology improvements, development processes, and engineering best practices.
Evaluate technical requirements and provide input on project scope, effort, and resource needs.
Work effectively within a collaborative, distributed engineering environment.
Mentor and provide technical guidance to less-experienced engineers.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent experience.
10+ years of industry experience in ASIC and/or SoC design.
Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
Demonstrated experience across multiple stages of the ASIC/SoC development flow.
Experience with synthesis and industry-standard EDA tools.
Strong understanding of digital design, timing, constraints, and implementation concepts.
Experience working with processor-based SoC designs or RISC architectures.
Proficiency in Linux/UNIX environments and scripting.
Experience with programming or scripting languages such as Python, Perl, Tcl, C/C++, or similar.
Familiarity with modern source-control systems and collaborative engineering workflows.
Strong analytical, problem-solving, and communication skills.
Ability to take ownership of technically challenging projects and work effectively in a team environment.
Demonstrated ability to mentor engineers and provide technical leadership.
Preferred Qualifications
Experience with radiation-tolerant or reliability-focused semiconductor design.
Analog/mixed-signal design experience or familiarity with mixed-signal development environments.
Experience with standard-cell libraries or related semiconductor IP.
Experience taking complex ASIC/SoC designs successfully through fabrication.
Familiarity with additional EDA tools and advanced design methodologies.
Salary of $150,000 to $205,000 annually (salary depends on experience level, education and qualifications)
Show more Show less