CL
IC Layout Design
Accepting applicationsCirrus Logic · Greensboro, NC
Full-Time Mid_senior CMOSCadenceCalibreMentoranalog
Posted
1d ago
Category
Eda
Experience
Mid_senior
Country
United States
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
The Role
In this position, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and Mentor's Calibre tools, and work with circuit engineers to generate topological layouts to ensure optimal circuit performance.
Responsibilities
Solving layout design issues and applying proactive intervention
Proactively work with design engineers to achieve efficient circuit performance
Design analog & mixed-signal layouts
Understand device matching techniques
Understand signal conditioning/protection techniques
Strong collaboration skills, including written and verbal communication
Outstanding layout planning and integration skills
Experience in routing at the block level and chip top-level using assisted/automated tools
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.
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The Role
In this position, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and Mentor's Calibre tools, and work with circuit engineers to generate topological layouts to ensure optimal circuit performance.
Responsibilities
Solving layout design issues and applying proactive intervention
Proactively work with design engineers to achieve efficient circuit performance
Design analog & mixed-signal layouts
Understand device matching techniques
Understand signal conditioning/protection techniques
Strong collaboration skills, including written and verbal communication
Outstanding layout planning and integration skills
Experience in routing at the block level and chip top-level using assisted/automated tools
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.
Show more Show less