MT
Foundry PDK / Collateral Integration Engineer (CAD/EDA)
Accepting applicationsMicron Technology · Richardson, TX
Full-Time Associate AIASICCadenceCalibrePerl
Posted
3d ago
Category
Eda
Experience
Associate
Country
United States
Foundry PDK / Collateral Integration Engineer (CAD/EDA)
📍 Richardson, TX (Hybrid/Onsite)
💼 Senior Engineer / Staff Engineer Level
🏢 Semiconductor | Advanced Packaging | AI Infrastructure
About the Role
Artificial Intelligence is transforming the world, and advanced packaging and High Bandwidth Memory (HBM) technologies are at the center of that transformation. We are seeking an experienced Foundry PDK / Collateral Integration Engineer to support next-generation semiconductor and packaging technologies by enabling robust CAD/EDA design environments and foundry collateral integration.
In this role, you will work closely with foundries, IP providers, design teams, CAD engineers, and EDA vendors to ensure timely deployment, validation, and support of Process Design Kits (PDKs), rule decks, models, and technology collateral.
What You'll Do
PDK & Foundry Collateral Management
Coordinate acquisition of foundry collateral including PDKs, rule decks, models, libraries, and IP deliverables.
Manage secure distribution and access control for foundry-provided data.
Track collateral releases, versioning, and deployment schedules.
CAD Environment & Integration
Install, configure, and maintain PDKs in standardized design environments.
Integrate technology files, libraries, models, and physical verification decks.
Maintain multi-node and multi-foundry CAD infrastructure.
Validation & Qualification
Execute and maintain PDK validation methodologies.
Perform unit and regression testing for:
DRC
LVS
ERC
PERC
Extraction flows
SPICE models
Standard cell and IP libraries
Investigate and resolve collateral integration issues.
Automation & Productivity
Develop automation solutions using Python, TCL, SKILL, Perl, or Shell scripting.
Improve validation coverage and deployment efficiency through workflow automation.
Create documentation, user guides, and release notes.
Cross-Functional Collaboration
Partner with foundries, IP vendors, design teams, packaging engineers, and EDA suppliers.
Drive issue resolution and support tapeout readiness activities.
Provide technical guidance to engineering teams using new technology nodes.
Required Qualifications
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5+ years of semiconductor CAD/EDA, PDK, or physical verification experience.
Hands-on experience with foundry PDKs (TSMC, Intel Foundry, Samsung, GlobalFoundries, or similar).
Strong understanding of:
DRC
LVS
ERC
PERC
Extraction methodologies
Experience with industry-standard EDA tools:
Cadence Virtuoso
Calibre
Synopsys IC Validator (ICV)
Pegasus or equivalent
Proficiency in Linux/Unix environments.
Experience with Python, TCL, SKILL, Perl, or Shell scripting.
Preferred Qualifications
Advanced packaging, chiplet, 2.5D/3D integration, or HBM experience.
PDK development, qualification, or QA ownership.
Experience integrating:
Technology files
PCells/PyCells
SPICE models
Standard cell libraries
Physical verification rule decks
Experience collaborating directly with foundries and EDA vendors.
Knowledge of tapeout and signoff methodologies.
Why Join Us?
Work on cutting-edge AI and advanced packaging technologies.
Influence future semiconductor roadmaps.
Collaborate with leading foundries and EDA suppliers.
Join a highly visible engineering team driving innovation from R&D through manufacturing.
Competitive compensation, benefits, and career growth opportunities.
Interested? Apply today or message me directly to learn more about this exciting opportunity in Advanced Packaging and Foundry Enablement. #SemiconductorJobs #PDK #EDA #CAD #VLSI #PhysicalVerification #ASIC #HBM #AdvancedPackaging #Chiplets #TSMC #Calibre #Cadence #Synopsys #RichardsonTX
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📍 Richardson, TX (Hybrid/Onsite)
💼 Senior Engineer / Staff Engineer Level
🏢 Semiconductor | Advanced Packaging | AI Infrastructure
About the Role
Artificial Intelligence is transforming the world, and advanced packaging and High Bandwidth Memory (HBM) technologies are at the center of that transformation. We are seeking an experienced Foundry PDK / Collateral Integration Engineer to support next-generation semiconductor and packaging technologies by enabling robust CAD/EDA design environments and foundry collateral integration.
In this role, you will work closely with foundries, IP providers, design teams, CAD engineers, and EDA vendors to ensure timely deployment, validation, and support of Process Design Kits (PDKs), rule decks, models, and technology collateral.
What You'll Do
PDK & Foundry Collateral Management
Coordinate acquisition of foundry collateral including PDKs, rule decks, models, libraries, and IP deliverables.
Manage secure distribution and access control for foundry-provided data.
Track collateral releases, versioning, and deployment schedules.
CAD Environment & Integration
Install, configure, and maintain PDKs in standardized design environments.
Integrate technology files, libraries, models, and physical verification decks.
Maintain multi-node and multi-foundry CAD infrastructure.
Validation & Qualification
Execute and maintain PDK validation methodologies.
Perform unit and regression testing for:
DRC
LVS
ERC
PERC
Extraction flows
SPICE models
Standard cell and IP libraries
Investigate and resolve collateral integration issues.
Automation & Productivity
Develop automation solutions using Python, TCL, SKILL, Perl, or Shell scripting.
Improve validation coverage and deployment efficiency through workflow automation.
Create documentation, user guides, and release notes.
Cross-Functional Collaboration
Partner with foundries, IP vendors, design teams, packaging engineers, and EDA suppliers.
Drive issue resolution and support tapeout readiness activities.
Provide technical guidance to engineering teams using new technology nodes.
Required Qualifications
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5+ years of semiconductor CAD/EDA, PDK, or physical verification experience.
Hands-on experience with foundry PDKs (TSMC, Intel Foundry, Samsung, GlobalFoundries, or similar).
Strong understanding of:
DRC
LVS
ERC
PERC
Extraction methodologies
Experience with industry-standard EDA tools:
Cadence Virtuoso
Calibre
Synopsys IC Validator (ICV)
Pegasus or equivalent
Proficiency in Linux/Unix environments.
Experience with Python, TCL, SKILL, Perl, or Shell scripting.
Preferred Qualifications
Advanced packaging, chiplet, 2.5D/3D integration, or HBM experience.
PDK development, qualification, or QA ownership.
Experience integrating:
Technology files
PCells/PyCells
SPICE models
Standard cell libraries
Physical verification rule decks
Experience collaborating directly with foundries and EDA vendors.
Knowledge of tapeout and signoff methodologies.
Why Join Us?
Work on cutting-edge AI and advanced packaging technologies.
Influence future semiconductor roadmaps.
Collaborate with leading foundries and EDA suppliers.
Join a highly visible engineering team driving innovation from R&D through manufacturing.
Competitive compensation, benefits, and career growth opportunities.
Interested? Apply today or message me directly to learn more about this exciting opportunity in Advanced Packaging and Foundry Enablement. #SemiconductorJobs #PDK #EDA #CAD #VLSI #PhysicalVerification #ASIC #HBM #AdvancedPackaging #Chiplets #TSMC #Calibre #Cadence #Synopsys #RichardsonTX
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