SS
GLS Verification Engineer
Accepting applicationsSmartSoC Solutions Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior ATPGDFTJTAGPerlPython
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Experience: 3–8 Years
Location: Hyderabad,
Key Responsibilities
Execute Gate-Level Simulations (GLS) with zero-delay and SDF timing.
Debug setup/hold, recovery/removal, X-propagation, and timing violations.
Validate RTL-to-gate equivalence and synthesis/P&R impacts.
Perform SoC-level GLS for boot, reset, clocks, interrupts, and functional scenarios.
Verify low-power features such as UPF, isolation, retention, and level shifters.
Validate DFT/scan/ATPG/JTAG functionality at gate level.
Debug failures using VCS/Xcelium/Questa, Verdi/DVE and waveform analysis.
Correlate GLS failures with STA, RTL, synthesis, PD, and DFT results.
Automate GLS regressions using Python/Perl/Tcl/Shell.
Support pre-silicon signoff and tape-out readiness.
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Location: Hyderabad,
Key Responsibilities
Execute Gate-Level Simulations (GLS) with zero-delay and SDF timing.
Debug setup/hold, recovery/removal, X-propagation, and timing violations.
Validate RTL-to-gate equivalence and synthesis/P&R impacts.
Perform SoC-level GLS for boot, reset, clocks, interrupts, and functional scenarios.
Verify low-power features such as UPF, isolation, retention, and level shifters.
Validate DFT/scan/ATPG/JTAG functionality at gate level.
Debug failures using VCS/Xcelium/Questa, Verdi/DVE and waveform analysis.
Correlate GLS failures with STA, RTL, synthesis, PD, and DFT results.
Automate GLS regressions using Python/Perl/Tcl/Shell.
Support pre-silicon signoff and tape-out readiness.
Show more Show less