PA
Front-End Verification Infrastructure Engineer
Accepting applicationsProdapt ASIC services (Formerly Innovative Logic) · San Jose, CA
Full-Time Mid_senior AIASICAnalogDFTFPGA
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
About the Company
Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup, and Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 5,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.
The FE Infrastructure team is seeking a highly skilled, motivated Engineer to drive front-end flows, tools, and methodologies. This role requires deep technical expertise across multiple verification platforms and a proven track record of solving complex infrastructure challenges. You will spearhead regression management, tool deployment, and strategic collaborations with industry-leading EDA vendors to ensure seamless, scalable project continuity.
Key Responsibilities
Verification Flows: Design, scale, and maintain complex, automated FE Design Verification flows.
Regression Management: Lead regression management systems, troubleshoot pipeline bottlenecks, and triage coverage/fail issues.
EDA Vendor Relations: Act as primary contact for Synopsys VCS; liaise with EDA vendors to debug tools and resolve escalated issues.
Tool Deployment: Deploy and integrate RTL Architecture tools into primary front-end verification flows.
Version Control: Manage and optimize Git, Perforce, and Git-P4 workflows for development teams.
Required Qualifications
10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering or in a related field
Proven experience in designing, maintaining, and troubleshooting FE Design Verification flows and CAD infrastructure for large-scale, high-performance projects.
Expertise in flow-based regression management, with strong analytical skills in debugging regression and coverage issues.
Familiarity with industry-standard tools including Synopsys VCS, IES, and RTL architecture tools, with hands-on experience in xprop configuration for VCS and IES.
Advanced knowledge of version control systems, particularly Git, Perforce, and Git-P4 interfaces, with an ability to support and streamline versioning workflows.
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Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup, and Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 5,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.
The FE Infrastructure team is seeking a highly skilled, motivated Engineer to drive front-end flows, tools, and methodologies. This role requires deep technical expertise across multiple verification platforms and a proven track record of solving complex infrastructure challenges. You will spearhead regression management, tool deployment, and strategic collaborations with industry-leading EDA vendors to ensure seamless, scalable project continuity.
Key Responsibilities
Verification Flows: Design, scale, and maintain complex, automated FE Design Verification flows.
Regression Management: Lead regression management systems, troubleshoot pipeline bottlenecks, and triage coverage/fail issues.
EDA Vendor Relations: Act as primary contact for Synopsys VCS; liaise with EDA vendors to debug tools and resolve escalated issues.
Tool Deployment: Deploy and integrate RTL Architecture tools into primary front-end verification flows.
Version Control: Manage and optimize Git, Perforce, and Git-P4 workflows for development teams.
Required Qualifications
10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering or in a related field
Proven experience in designing, maintaining, and troubleshooting FE Design Verification flows and CAD infrastructure for large-scale, high-performance projects.
Expertise in flow-based regression management, with strong analytical skills in debugging regression and coverage issues.
Familiarity with industry-standard tools including Synopsys VCS, IES, and RTL architecture tools, with hands-on experience in xprop configuration for VCS and IES.
Advanced knowledge of version control systems, particularly Git, Perforce, and Git-P4 interfaces, with an ability to support and streamline versioning workflows.
Show more Show less