MT
FPGA Prototyping / Emulation Engineer
Accepting applicationsMirafra Technologies · San Francisco Bay Area
Full-Time Mid_senior ASICC++CadenceDDRFPGA
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Key Responsibilities
Develop and support FPGA prototyping and emulation flows for large-scale SoCs.
Convert and adapt ASIC RTL for FPGA implementation, including partitioning, synthesis, timing closure, and resource optimization.
Work with platforms such as Synopsys HAPS/ZeBu, Cadence Protium/Palladium, or Siemens Veloce.
Perform prototype bring-up, RTL debug, hardware debug, and performance optimization.
Enable pre-silicon software/firmware bring-up and HW/SW co-validation.
Debug issues involving clocks, resets, memories, interfaces, timing, and multi-FPGA communication.
Develop automation and infrastructure using Python, TCL, Perl, or Shell scripting.
Collaborate with RTL, DV, architecture, firmware, and software teams to resolve complex issues.
Analyze FPGA resource utilization, timing, compilation, and runtime performance.
Support regression, validation, documentation, and development of reusable prototyping methodologies.
Required Skills
5+ years of hands-on experience in FPGA prototyping and/or hardware emulation.
Strong knowledge of Verilog/SystemVerilog and digital design fundamentals.
Experience with FPGA synthesis, implementation, timing constraints, and timing closure.
Hands-on experience with Vivado, Quartus, Synplify, or equivalent tools.
Experience with HAPS, ZeBu, Palladium, Protium, or Veloce is highly preferred.
Strong debugging skills using waveform/debug tools and FPGA instrumentation.
Proficiency in Python/TCL/Perl/Shell scripting.
Good understanding of SoC architecture, clock/reset domains, and standard interfaces such as AXI/AMBA, PCIe, DDR, USB, CXL, or similar.
Experience with C/C++/SystemC, UVM, or firmware/software bring-up is a plus.
Strong analytical, communication, and problem-solving skills.
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Develop and support FPGA prototyping and emulation flows for large-scale SoCs.
Convert and adapt ASIC RTL for FPGA implementation, including partitioning, synthesis, timing closure, and resource optimization.
Work with platforms such as Synopsys HAPS/ZeBu, Cadence Protium/Palladium, or Siemens Veloce.
Perform prototype bring-up, RTL debug, hardware debug, and performance optimization.
Enable pre-silicon software/firmware bring-up and HW/SW co-validation.
Debug issues involving clocks, resets, memories, interfaces, timing, and multi-FPGA communication.
Develop automation and infrastructure using Python, TCL, Perl, or Shell scripting.
Collaborate with RTL, DV, architecture, firmware, and software teams to resolve complex issues.
Analyze FPGA resource utilization, timing, compilation, and runtime performance.
Support regression, validation, documentation, and development of reusable prototyping methodologies.
Required Skills
5+ years of hands-on experience in FPGA prototyping and/or hardware emulation.
Strong knowledge of Verilog/SystemVerilog and digital design fundamentals.
Experience with FPGA synthesis, implementation, timing constraints, and timing closure.
Hands-on experience with Vivado, Quartus, Synplify, or equivalent tools.
Experience with HAPS, ZeBu, Palladium, Protium, or Veloce is highly preferred.
Strong debugging skills using waveform/debug tools and FPGA instrumentation.
Proficiency in Python/TCL/Perl/Shell scripting.
Good understanding of SoC architecture, clock/reset domains, and standard interfaces such as AXI/AMBA, PCIe, DDR, USB, CXL, or similar.
Experience with C/C++/SystemC, UVM, or firmware/software bring-up is a plus.
Strong analytical, communication, and problem-solving skills.
Show more Show less