FPGA Engineer

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟴𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟱-𝟴 𝗟𝗣𝗔)

Experience: 2+ yrs

Location: chennai,hyderabad,bangalore

Job Type: Full-time

We are looking for a skilled FPGA Design Verification Engineer with hands-on experience in the Xilinx Vivado implementation flow to validate and test FPGA implementation stages, including placement and Static Timing Analysis (STA).

The ideal candidate will have a strong understanding of FPGA design flows, digital and logic design, STA, design constraints, and debugging. You will be responsible for validating implementation flows, identifying issues, analysing results, and collaborating with engineering teams to ensure reliable and efficient FPGA designs.

Requirements

Key Responsibilities

Validate and test Xilinx Vivado FPGA implementation flows across different stages
Work with Vivado implementation stages including placement and Static Timing Analysis (STA)
Analyse implementation results and identify potential design, timing, and flow-related issues
Validate FPGA designs against defined implementation and timing requirements
Perform Static Timing Analysis and analyse timing reports, paths, violations, and constraints
Work with design constraints and verify their correctness and impact on implementation
Debug logic, timing, placement, and implementation-related issues
Analyse failures and collaborate with design and verification teams to identify root causes
Develop and execute test scenarios to validate Vivado implementation functionality and robustness
Support FPGA design-flow validation across different design configurations and use cases
Collaborate with digital design, FPGA, verification, and EDA teams to resolve technical issues
Review implementation reports and provide actionable technical feedback
Contribute to improving implementation-flow validation, testing methodologies, and debug processes
Explore opportunities for test automation and scripting to improve validation efficiency
Leverage emerging AI-assisted tools and techniques where appropriate to improve engineering productivity
Document test results, issues, debug findings, and validation methodologies

What Makes You a Great Fit

2-4 years of experience in FPGA design, FPGA verification, EDA, digital design, or a related engineering domain
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), Electronics & Instrumentation (EI), VLSI, or a related discipline
Hands-on experience with Xilinx Vivado, particularly the Vivado Implementation tool flow
Strong understanding of the FPGA design and implementation flow
Good knowledge of Static Timing Analysis (STA) and timing analysis methodologies
Strong fundamentals in digital design and logic design
Understanding of design constraints, timing constraints, and their application in FPGA implementation
Strong debugging and problem-solving skills with the ability to analyse complex implementation issues
Experience interpreting Vivado reports and identifying timing, placement, and implementation problems
Ability to understand system-level design concepts and their impact on FPGA implementation
Experience with an EDA company or EDA tool development/validation environment is an advantage
Knowledge of scripting or test automation is desirable
Familiarity with AI-assisted engineering or AI productivity tools is a plus
Strong analytical skills and attention to detail
Good communication and collaboration skills with the ability to work effectively across engineering teams
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