LT
Electrical Design Engineer
Accepting applicationsL&T Technology Services · Dublin, CA
Full-Time Mid_senior ARMEthernetFPGAI2CMixed signal
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
Ireland
Key Responsibilities:
Design & Development: Mixed signal design, analog and digital
High-Speed Board Design: Routing and layout for high-speed memory and interfaces like DDR3/DDR4, PCIe, and QSPI with strict impedance control.
Power Tree Architecture: Designing complex DC-DC power management networks utilizing buck and boost regulators, low-dropout (LDO) regulators, and sequencing.
Processor & FPGA Ecosystems: Architecting systems around advanced microprocessors, microcontrollers (ARM Cortex-M, RISC-V), and FPGAs. Signal Integrity & EMI/EMC: Mitigating noise, crosstalk, and electromagnetic interference to ensure regulatory compliance (FCC, CE, automotive/aerospace standards).
Protocols & Lab Verification - Bus Interfaces: Deep mastery of low-to-high-speed communication protocols including I2C, SPI, UART, RS485, CAN, USB, and Ethernet.
Advanced Lab Instrumentation: Expert usage of digital storage oscilloscopes (DSO), logic analyzers, vector network analyzers (VNA), and spectrum analyzers. Root-Cause Analysis:
Advanced troubleshooting down to the component level, performing de-rating analysis, and thermal management.
Leadership & Project Lifecycle Team & Technical Leadership: Mentoring junior/mid-level engineers, driving design reviews, and managing cross-functional dependencies with firmware, mechanical, and software teams.
Project Management: Creating architectural trade-off analyses, component selection matrices, project scheduling, and budgeting.
Schematic & PCB Tools: Proficiency with enterprise EDA tools such as Xpedition
Qualification:
B.E / M.S / Mtech
Paid Leave, Health Insurance, Group life insurance, Disability, 401(K)
The expected salary range for this position is between $70,000 to $1,32,500 annually. The actual salary may vary based upon several factors including, but not limited to, relevant skills/experience, time in role, base salary of internal peers, prior performance, business line, and geographic/office location.
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Design & Development: Mixed signal design, analog and digital
High-Speed Board Design: Routing and layout for high-speed memory and interfaces like DDR3/DDR4, PCIe, and QSPI with strict impedance control.
Power Tree Architecture: Designing complex DC-DC power management networks utilizing buck and boost regulators, low-dropout (LDO) regulators, and sequencing.
Processor & FPGA Ecosystems: Architecting systems around advanced microprocessors, microcontrollers (ARM Cortex-M, RISC-V), and FPGAs. Signal Integrity & EMI/EMC: Mitigating noise, crosstalk, and electromagnetic interference to ensure regulatory compliance (FCC, CE, automotive/aerospace standards).
Protocols & Lab Verification - Bus Interfaces: Deep mastery of low-to-high-speed communication protocols including I2C, SPI, UART, RS485, CAN, USB, and Ethernet.
Advanced Lab Instrumentation: Expert usage of digital storage oscilloscopes (DSO), logic analyzers, vector network analyzers (VNA), and spectrum analyzers. Root-Cause Analysis:
Advanced troubleshooting down to the component level, performing de-rating analysis, and thermal management.
Leadership & Project Lifecycle Team & Technical Leadership: Mentoring junior/mid-level engineers, driving design reviews, and managing cross-functional dependencies with firmware, mechanical, and software teams.
Project Management: Creating architectural trade-off analyses, component selection matrices, project scheduling, and budgeting.
Schematic & PCB Tools: Proficiency with enterprise EDA tools such as Xpedition
Qualification:
B.E / M.S / Mtech
Paid Leave, Health Insurance, Group life insurance, Disability, 401(K)
The expected salary range for this position is between $70,000 to $1,32,500 annually. The actual salary may vary based upon several factors including, but not limited to, relevant skills/experience, time in role, base salary of internal peers, prior performance, business line, and geographic/office location.
Show more Show less