PI
DSP & Algorithm Engineer (Electrical/Optical SerDes)
Accepting applicationsPER International · San Jose, CA
Full-Time Mid_senior C++EthernetMATLABPCIePython
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Electrical / Optical SerDes DSP & Algorithm Engineer
Location: San Jose, CA or Irvine, CA (4 days on-site)
Our client is looking for an experienced DSP and communications engineer to join a team developing advanced algorithms and architectures for next-generation high-speed electrical and optical SerDes. This is a highly technical, hands-on position focused on algorithm development, system modeling, architecture optimization, and implementation support. More senior candidates may operate as technical leads or managers but are expected to remain closely involved in hands-on technical development
Key Responsibilities:
Develop advanced DSP algorithms and architectures for high-speed electrical and optical SerDes systems.
Develop system and algorithm models using MATLAB, Python and/or C++ to evaluate performance and architectural trade-offs.
Develop and optimize algorithms for areas including equalization, timing recovery/CDR, compensation, cancellation, sequence detection, and channel coding/FEC.
Model analog front-end (AFE) impairments and develop DSP-based techniques to compensate for their impact on system performance.
Optimize algorithms and architectures for power, performance and area (PPA).
Support the transition from floating-point algorithm concepts into implementation-oriented and bit-true/cycle-true models.
Work closely with digital, analog, RTL, verification and system teams throughout the design lifecycle.
Support design verification, silicon bring-up, debugging and post-silicon validation.
Collaborate with engineering teams across multiple international locations.
Provide technical leadership and architectural direction where appropriate to experience level.
Requirements
Deep understanding of digital signal processing (DSP), communication theory and high-speed communication systems.
Strong experience in wireline and/or optical communications.
Experience developing or architecting DSP algorithms for high-speed SerDes or related communication systems.
Strong system modeling capability using MATLAB, Python and/or C++.
Relevant technical experience may include:
Optical communications / optical DSP
Electrical SerDes
Ethernet PHY
PCIe / CXL
Coherent communications
Equalization / FFE / DFE
CDR / timing recovery
Adaptation algorithms
Coding / FEC
Sequence detection
Compensation and cancellation algorithms
AFE impairment modeling and DSP-based compensation
Experience taking algorithms from initial concept and modeling through implementation and validation is highly valued.
Experience with analog circuit design and/or RTL design is advantageous.
Strong communication skills and ability to work effectively across multidisciplinary and geographically distributed engineering teams.
MS or PhD in Electrical Engineering, Computer Science or a related discipline.
Please reach out to [email protected] for more details or to express interest in the role.
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Location: San Jose, CA or Irvine, CA (4 days on-site)
Our client is looking for an experienced DSP and communications engineer to join a team developing advanced algorithms and architectures for next-generation high-speed electrical and optical SerDes. This is a highly technical, hands-on position focused on algorithm development, system modeling, architecture optimization, and implementation support. More senior candidates may operate as technical leads or managers but are expected to remain closely involved in hands-on technical development
Key Responsibilities:
Develop advanced DSP algorithms and architectures for high-speed electrical and optical SerDes systems.
Develop system and algorithm models using MATLAB, Python and/or C++ to evaluate performance and architectural trade-offs.
Develop and optimize algorithms for areas including equalization, timing recovery/CDR, compensation, cancellation, sequence detection, and channel coding/FEC.
Model analog front-end (AFE) impairments and develop DSP-based techniques to compensate for their impact on system performance.
Optimize algorithms and architectures for power, performance and area (PPA).
Support the transition from floating-point algorithm concepts into implementation-oriented and bit-true/cycle-true models.
Work closely with digital, analog, RTL, verification and system teams throughout the design lifecycle.
Support design verification, silicon bring-up, debugging and post-silicon validation.
Collaborate with engineering teams across multiple international locations.
Provide technical leadership and architectural direction where appropriate to experience level.
Requirements
Deep understanding of digital signal processing (DSP), communication theory and high-speed communication systems.
Strong experience in wireline and/or optical communications.
Experience developing or architecting DSP algorithms for high-speed SerDes or related communication systems.
Strong system modeling capability using MATLAB, Python and/or C++.
Relevant technical experience may include:
Optical communications / optical DSP
Electrical SerDes
Ethernet PHY
PCIe / CXL
Coherent communications
Equalization / FFE / DFE
CDR / timing recovery
Adaptation algorithms
Coding / FEC
Sequence detection
Compensation and cancellation algorithms
AFE impairment modeling and DSP-based compensation
Experience taking algorithms from initial concept and modeling through implementation and validation is highly valued.
Experience with analog circuit design and/or RTL design is advantageous.
Strong communication skills and ability to work effectively across multidisciplinary and geographically distributed engineering teams.
MS or PhD in Electrical Engineering, Computer Science or a related discipline.
Please reach out to [email protected] for more details or to express interest in the role.
Show more Show less