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Design Verification Engineer – SystemVerilog/UVM
Accepting applicationsIntellectt Inc · San Jose, CA
Full-Time Mid_senior AIASICC++PythonRTL
Posted
20h ago
Category
Design
Experience
Mid_senior
Country
United States
Location: San Jose, CA
Employment Type: Full-time / Direct Hire
Duration: Permanent
Salary: The salary for this position is $160K/Annum
Benefits: Benefits will be provided by the hiring client in accordance with their policies.
Job Summary:
We are seeking a skilled Design Verification Engineer to verify complex internal IP blocks, including compute engines, accelerators, and custom logic within SoC environments. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM, RTL/block-level verification, functional and code coverage, and RTL/testbench debugging.
Key Responsibilities:
Develop and maintain SystemVerilog/UVM-based verification environments.
Perform block-level functional verification of RTL designs.
Create detailed test plans, test cases, and coverage models.
Develop directed and constrained-random tests.
Develop functional and code coverage strategies and drive coverage closure.
Debug RTL and testbench issues using simulation, waveform analysis, and debug tools such as Verdi/DVE.
Develop and maintain verification components including drivers, monitors, sequencers, scoreboards, and reference models.
Develop and utilize SystemVerilog Assertions (SVA) for functional and protocol verification.
Collaborate with RTL designers and verification teams to identify, debug, and resolve design issues.
Support regression testing and verification signoff.
Required Qualifications:
BS/MS degree in EE, ECE, CE, or a related field.
3–8+ years of Design Verification experience.
Hands-on experience with SystemVerilog and UVM.
Experience with ASIC/SoC/IP and block-level verification.
Strong understanding of digital design and RTL fundamentals.
Experience creating test plans and test cases.
Experience with functional and code coverage and driving coverage closure.
Strong RTL/testbench debugging skills.
Experience with Verdi, DVE, or similar debug tools.
Preferred Qualifications:
Experience with SoC verification.
Experience with AMBA protocols, including AXI, AHB, and APB.
Experience with SVA/Assertions and constrained-random verification.
Experience with UPF/low-power verification.
Experience verifying AI/ML accelerators, compute engines, CPU/GPU, networking, or custom ASIC IP.
Programming experience with Python and/or C++.
Exposure to formal verification.
Equal Opportunity Employer:
We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.
Background Check: Background checks may be conducted in accordance with applicable laws.
Work Authorization: Applicants must be authorized to work in the United States.
Show more Show less
Employment Type: Full-time / Direct Hire
Duration: Permanent
Salary: The salary for this position is $160K/Annum
Benefits: Benefits will be provided by the hiring client in accordance with their policies.
Job Summary:
We are seeking a skilled Design Verification Engineer to verify complex internal IP blocks, including compute engines, accelerators, and custom logic within SoC environments. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM, RTL/block-level verification, functional and code coverage, and RTL/testbench debugging.
Key Responsibilities:
Develop and maintain SystemVerilog/UVM-based verification environments.
Perform block-level functional verification of RTL designs.
Create detailed test plans, test cases, and coverage models.
Develop directed and constrained-random tests.
Develop functional and code coverage strategies and drive coverage closure.
Debug RTL and testbench issues using simulation, waveform analysis, and debug tools such as Verdi/DVE.
Develop and maintain verification components including drivers, monitors, sequencers, scoreboards, and reference models.
Develop and utilize SystemVerilog Assertions (SVA) for functional and protocol verification.
Collaborate with RTL designers and verification teams to identify, debug, and resolve design issues.
Support regression testing and verification signoff.
Required Qualifications:
BS/MS degree in EE, ECE, CE, or a related field.
3–8+ years of Design Verification experience.
Hands-on experience with SystemVerilog and UVM.
Experience with ASIC/SoC/IP and block-level verification.
Strong understanding of digital design and RTL fundamentals.
Experience creating test plans and test cases.
Experience with functional and code coverage and driving coverage closure.
Strong RTL/testbench debugging skills.
Experience with Verdi, DVE, or similar debug tools.
Preferred Qualifications:
Experience with SoC verification.
Experience with AMBA protocols, including AXI, AHB, and APB.
Experience with SVA/Assertions and constrained-random verification.
Experience with UPF/low-power verification.
Experience verifying AI/ML accelerators, compute engines, CPU/GPU, networking, or custom ASIC IP.
Programming experience with Python and/or C++.
Exposure to formal verification.
Equal Opportunity Employer:
We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.
Background Check: Background checks may be conducted in accordance with applicable laws.
Work Authorization: Applicants must be authorized to work in the United States.
Show more Show less