IR
Design Engineer
Accepting applicationsIC Resources · Irvine, CA
Full-Time Mid_senior C++CadenceGenusMatlabRTL
Posted
20h ago
Category
Eda
Experience
Mid_senior
Country
United States
We're hiring: Design Engineer
Join an elite team working at the cutting edge of wireless communications technology, developing IP, system, and board solutions that push the capabilities of 5G forward.
This is a hands on role where you'll play a real part in growing our product portfolio, not just executing someone else's roadmap.
What you'll work on:
Architecture, design, development, verification and documentation of our IP RTL implementations of communication electronics systems using SystemVerilog
Testbench development for RTL implementations
What we're looking for:
4+ years of relevant industry experience, degree qualified
EDA tools for simulation and synthesis (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus)
AXI interfacing experience
Timing and hardware resource optimization for high throughput signal processing
C/C++/Matlab prototyping for design and verification
Solid version control practices (Git) and documentation habits (Confluence)
Bonus points for EDA tooling admin experience, automation (Jenkins), or knowledge of communications signal processing (error correction, equalization, channel estimation, beamforming)
We're looking for someone highly capable, motivated, and commercially savvy, someone who builds trust quickly and communicates clearly across technical and non technical stakeholders alike.
If you want to help shape the next generation of global wireless connectivity, this is your seat at the table.
Interested or know someone who'd be a fit? Send a message or drop a note below.
Show more Show less
Join an elite team working at the cutting edge of wireless communications technology, developing IP, system, and board solutions that push the capabilities of 5G forward.
This is a hands on role where you'll play a real part in growing our product portfolio, not just executing someone else's roadmap.
What you'll work on:
Architecture, design, development, verification and documentation of our IP RTL implementations of communication electronics systems using SystemVerilog
Testbench development for RTL implementations
What we're looking for:
4+ years of relevant industry experience, degree qualified
EDA tools for simulation and synthesis (ModelSim, Quartus, Vivado, Synopsys DC, Cadence Genus)
AXI interfacing experience
Timing and hardware resource optimization for high throughput signal processing
C/C++/Matlab prototyping for design and verification
Solid version control practices (Git) and documentation habits (Confluence)
Bonus points for EDA tooling admin experience, automation (Jenkins), or knowledge of communications signal processing (error correction, equalization, channel estimation, beamforming)
We're looking for someone highly capable, motivated, and commercially savvy, someone who builds trust quickly and communicates clearly across technical and non technical stakeholders alike.
If you want to help shape the next generation of global wireless connectivity, this is your seat at the table.
Interested or know someone who'd be a fit? Send a message or drop a note below.
Show more Show less