TE
Customer Enablement/Design Enablement Engineer
Accepting applicationsTata Electronics · Bengaluru, Karnataka, India
Full-Time Associate AICadenceCalibreInnovusPython
Posted
19h ago
Category
Eda
Experience
Associate
Country
India
About Tata Electronics:
Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.
Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust
About the Role:
The Design Enablement Engineer will play a critical role in enabling customers to successfully adopt and implement our semiconductor technologies. This position focuses on releasing high-quality Process Design Kits (PDKs), developing robust design methodologies, and ensuring seamless integration of foundry offerings into customer design environments. The engineer will work closely with internal and external stakeholders to deliver comprehensive design enablement collateral and support optimal design decision-making across technology nodes.
Release and maintain PDKs, including design rules, models, and collateral, along with periodic updates.
Provide detailed insights into fab technology offerings and IP portfolios to guide customer design choices.
Deliver reference flows to accelerate design adoption and ensure consistency with foundry methodologies.
Create and maintain design enablement collateral to support customer onboarding and implementation.
The role also involves end-to-end design flow enablement from RTL to GDSII, ensuring robust, scalable, and high-quality implementation flows. The engineer will develop, qualify, and optimize digital design methodologies across synthesis, place and route, extraction, timing, and physical verification, while leveraging automation and benchmarking techniques to ensure flow reliability and performance across tools and technology nodes.
Drive RTL-to-GDSII flow creation, qualification, and optimization for successful tapeouts.
Collaborate with customers to debug and resolve DRC, LVS, and sign-off issues for clean tapeout databases.
Collaborate with EDA vendors and PDK teams to define, customize, and validate digital design flows.
Develop automation scripts (e.g., TCL, Python) for flow regression, error analysis, and metrics tracking.
Perform cross-tool benchmarking and PPA (Power, Performance, Area) comparisons using reference flows.
In addition, the Design Enablement Engineer will serve as a key technical interface with customers, ensuring their success through proactive support and continuous improvement initiatives. The role requires close collaboration with customers to resolve design issues, as well as internal coordination with PDK, IP, and CAD teams to enhance deliverables, flows, and overall design infrastructure.
Analyse customer feedback and translate it into actionable improvements for PDKs and design flows.
Work cross-functionally with internal teams to enhance design infrastructure and enablement quality. Continuously refine methodologies and collateral to improve customer productivity and success rate.
Required Skills and Tool Expertise:
Bachelor’s / Master’s in Electronics, Electrical, Semiconductor, Materials or related fields.
8+ years of hands‑on experience in physical design, implementation, and sign‑off.
Deep understanding of advanced design flows, reference methodologies, customer enablement and support, with proven tapeout experience.
Strong expertise in industry‑standard EDA tools such as Cadence Innovus, Synopsys DC/ICC2, Calibre, PrimeTime, and related sign‑off tools.
Excellent problem‑solving and communication skills, with the ability to interface directly with customers and cross‑functional teams.
Show more Show less
Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.
Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust
About the Role:
The Design Enablement Engineer will play a critical role in enabling customers to successfully adopt and implement our semiconductor technologies. This position focuses on releasing high-quality Process Design Kits (PDKs), developing robust design methodologies, and ensuring seamless integration of foundry offerings into customer design environments. The engineer will work closely with internal and external stakeholders to deliver comprehensive design enablement collateral and support optimal design decision-making across technology nodes.
Release and maintain PDKs, including design rules, models, and collateral, along with periodic updates.
Provide detailed insights into fab technology offerings and IP portfolios to guide customer design choices.
Deliver reference flows to accelerate design adoption and ensure consistency with foundry methodologies.
Create and maintain design enablement collateral to support customer onboarding and implementation.
The role also involves end-to-end design flow enablement from RTL to GDSII, ensuring robust, scalable, and high-quality implementation flows. The engineer will develop, qualify, and optimize digital design methodologies across synthesis, place and route, extraction, timing, and physical verification, while leveraging automation and benchmarking techniques to ensure flow reliability and performance across tools and technology nodes.
Drive RTL-to-GDSII flow creation, qualification, and optimization for successful tapeouts.
Collaborate with customers to debug and resolve DRC, LVS, and sign-off issues for clean tapeout databases.
Collaborate with EDA vendors and PDK teams to define, customize, and validate digital design flows.
Develop automation scripts (e.g., TCL, Python) for flow regression, error analysis, and metrics tracking.
Perform cross-tool benchmarking and PPA (Power, Performance, Area) comparisons using reference flows.
In addition, the Design Enablement Engineer will serve as a key technical interface with customers, ensuring their success through proactive support and continuous improvement initiatives. The role requires close collaboration with customers to resolve design issues, as well as internal coordination with PDK, IP, and CAD teams to enhance deliverables, flows, and overall design infrastructure.
Analyse customer feedback and translate it into actionable improvements for PDKs and design flows.
Work cross-functionally with internal teams to enhance design infrastructure and enablement quality. Continuously refine methodologies and collateral to improve customer productivity and success rate.
Required Skills and Tool Expertise:
Bachelor’s / Master’s in Electronics, Electrical, Semiconductor, Materials or related fields.
8+ years of hands‑on experience in physical design, implementation, and sign‑off.
Deep understanding of advanced design flows, reference methodologies, customer enablement and support, with proven tapeout experience.
Strong expertise in industry‑standard EDA tools such as Cadence Innovus, Synopsys DC/ICC2, Calibre, PrimeTime, and related sign‑off tools.
Excellent problem‑solving and communication skills, with the ability to interface directly with customers and cross‑functional teams.
Show more Show less