LT
CPU Physical Design Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceDFTInnovusPerlPython
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
CPU Physical Design Engineer
Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a CPU Physical Design Engineer with strong hands-on expertise in implementing high-performance CPU cores and complex SoC blocks. The role involves driving physical implementation, timing closure, PPA optimization, and signoff for performance-critical CPU designs.
Key Responsibilities
Own physical implementation from netlist to GDSII across floorplanning, placement, CTS, routing, optimization, and signoff.
Work on high-performance CPU cores, critical datapaths, and timing-sensitive blocks.
Drive timing closure across complex MMMC scenarios with aggressive performance targets.
Analyze and optimize setup/hold, clock skew, congestion, buffering, transition, capacitance, and signal integrity issues.
Perform PPA optimization with focus on frequency, power, and area.
Drive clock-tree synthesis and optimization, including skew, latency, useful skew, and clock quality.
Execute physical ECOs and timing ECOs to achieve signoff targets.
Debug issues across RTL, synthesis, constraints, physical implementation, and STA.
Work closely with CPU Architecture, RTL, STA, Synthesis, DFT, and Signoff teams.
Contribute to physical design methodology, automation, and flow optimization.
Support full-chip integration and top-level timing closure for CPU/SoC designs.
Core Technical Requirements
6–12 years of hands-on Physical Design experience.
Strong experience with CPU / high-performance digital designs.
Deep understanding of floorplanning, placement, CTS, routing, optimization, and physical signoff.
Strong expertise in STA, timing analysis, and timing closure.
Experience with MMMC, SDC constraints, PVT corners, OCV/AOCV/POCV, and timing methodologies.
Strong understanding of clock architecture, skew optimization, clock gating, and CTS.
Experience debugging setup/hold violations, congestion, SI/crosstalk, transition and capacitance issues.
Hands-on experience with industry-standard tools such as Cadence Innovus and/or Synopsys ICC2.
Strong understanding of CPU critical paths, datapath optimization, and high-frequency design challenges.
Experience with physical and timing ECO implementation.
Strong scripting skills in Tcl; Python/Perl is a plus.
Preferred
Experience with advanced-node CPU designs.
Full-chip/top-level physical design experience.
Exposure to IR/EM, power analysis, signal integrity, and physical verification.
Experience with PrimeTime/Tempus and signoff flows.
Experience optimizing designs for high frequency and low power.
Strong understanding of CPU floorplanning, hierarchical implementation, and block-to-top timing interaction.
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Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a CPU Physical Design Engineer with strong hands-on expertise in implementing high-performance CPU cores and complex SoC blocks. The role involves driving physical implementation, timing closure, PPA optimization, and signoff for performance-critical CPU designs.
Key Responsibilities
Own physical implementation from netlist to GDSII across floorplanning, placement, CTS, routing, optimization, and signoff.
Work on high-performance CPU cores, critical datapaths, and timing-sensitive blocks.
Drive timing closure across complex MMMC scenarios with aggressive performance targets.
Analyze and optimize setup/hold, clock skew, congestion, buffering, transition, capacitance, and signal integrity issues.
Perform PPA optimization with focus on frequency, power, and area.
Drive clock-tree synthesis and optimization, including skew, latency, useful skew, and clock quality.
Execute physical ECOs and timing ECOs to achieve signoff targets.
Debug issues across RTL, synthesis, constraints, physical implementation, and STA.
Work closely with CPU Architecture, RTL, STA, Synthesis, DFT, and Signoff teams.
Contribute to physical design methodology, automation, and flow optimization.
Support full-chip integration and top-level timing closure for CPU/SoC designs.
Core Technical Requirements
6–12 years of hands-on Physical Design experience.
Strong experience with CPU / high-performance digital designs.
Deep understanding of floorplanning, placement, CTS, routing, optimization, and physical signoff.
Strong expertise in STA, timing analysis, and timing closure.
Experience with MMMC, SDC constraints, PVT corners, OCV/AOCV/POCV, and timing methodologies.
Strong understanding of clock architecture, skew optimization, clock gating, and CTS.
Experience debugging setup/hold violations, congestion, SI/crosstalk, transition and capacitance issues.
Hands-on experience with industry-standard tools such as Cadence Innovus and/or Synopsys ICC2.
Strong understanding of CPU critical paths, datapath optimization, and high-frequency design challenges.
Experience with physical and timing ECO implementation.
Strong scripting skills in Tcl; Python/Perl is a plus.
Preferred
Experience with advanced-node CPU designs.
Full-chip/top-level physical design experience.
Exposure to IR/EM, power analysis, signal integrity, and physical verification.
Experience with PrimeTime/Tempus and signoff flows.
Experience optimizing designs for high frequency and low power.
Strong understanding of CPU floorplanning, hierarchical implementation, and block-to-top timing interaction.
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