LI
ASIC Synthesis & STA Engineer ( Static Timing Analysis )
Accepting applicationsLanceSoft, Inc. · San Jose, CA
Full-Time Mid_senior ASICRTLSynopsys
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title - ASIC Synthesis + STA Engineer
Job Location- San Jose-CA
Experienced Required - 5+ Years
Job Type - Full Time with Benefits
Job Summary:
We are seeking a Synthesis / Static Timing Analysis (STA) Engineer to support full chip and block-level design implementation. This role will focus on constraints development, synthesis, timing analysis, and cross-functional collaboration to achieve timing closure and ensure design quality.
Key Responsibilities:
Develop full chip and block-level timing constraints
Perform synthesis and static timing analysis (STA) using Synopsys tools, including Primetime and Design Compiler
Execute timing closure activities and support DMSA flows
Run and debug Formality and VCLP tools to validate design correctness
Collaborate with Design, IP, Library, PNR, and RTL teams to support implementation and power intent requirements
Contribute to methodology and flow development for synthesis, formal verification, STA, and timing closure
Qualifications:
Experience with synthesis, STA, and timing closure methodologies
Hands-on experience with Synopsys Primetime, Design Compiler, DMSA flow, Formality, and VCLP
Strong timing constraint development experience
Ability to collaborate across multiple engineering teams
Strong problem-solving and debugging skills
Show more Show less
Job Location- San Jose-CA
Experienced Required - 5+ Years
Job Type - Full Time with Benefits
Job Summary:
We are seeking a Synthesis / Static Timing Analysis (STA) Engineer to support full chip and block-level design implementation. This role will focus on constraints development, synthesis, timing analysis, and cross-functional collaboration to achieve timing closure and ensure design quality.
Key Responsibilities:
Develop full chip and block-level timing constraints
Perform synthesis and static timing analysis (STA) using Synopsys tools, including Primetime and Design Compiler
Execute timing closure activities and support DMSA flows
Run and debug Formality and VCLP tools to validate design correctness
Collaborate with Design, IP, Library, PNR, and RTL teams to support implementation and power intent requirements
Contribute to methodology and flow development for synthesis, formal verification, STA, and timing closure
Qualifications:
Experience with synthesis, STA, and timing closure methodologies
Hands-on experience with Synopsys Primetime, Design Compiler, DMSA flow, Formality, and VCLP
Strong timing constraint development experience
Ability to collaborate across multiple engineering teams
Strong problem-solving and debugging skills
Show more Show less