TI
ASIC/RTL Design Engineer 5
Accepting applicationsTrilyon, Inc. · San Jose, CA
Contract Mid_senior ARMASICCMOSDDREthernet
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title: ASIC/RTL Design Engineer 5
Location – 2100 Logic Dr, San Jose, CA
Contract Term: 6 Months
Job Description
JOB DUTIES:
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs.
Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION:
SoC Architecture
Knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
Working knowledge of ARM cores and other I/O standard interfaces.
An ideal candidate would also exhibit: Strong communication and documentation skills,
Good organizational, time management and multitasking skills,
Strong initiative and discipline to follow-through,
Technical leadership.
10+ years of experience.
Show more Show less
Location – 2100 Logic Dr, San Jose, CA
Contract Term: 6 Months
Job Description
JOB DUTIES:
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs.
Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION:
SoC Architecture
Knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
Working knowledge of ARM cores and other I/O standard interfaces.
An ideal candidate would also exhibit: Strong communication and documentation skills,
Good organizational, time management and multitasking skills,
Strong initiative and discipline to follow-through,
Technical leadership.
10+ years of experience.
Show more Show less