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ASIC Principal Design Engineer
Accepting applicationsMacroHire · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICEthernetRTLSynopsysVerilog
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
Designation-ASIC Principal Design Engineer
Exp-10+ yrs
Location- Bangalore
JD-
Responsibilities:
Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
Required Skills:
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required with 8 plus years of experience
Show more Show less
Exp-10+ yrs
Location- Bangalore
JD-
Responsibilities:
Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
Required Skills:
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required with 8 plus years of experience
Show more Show less